https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/

[BML_sump2] / sump2 / impl / impl_syn.prj

diff --git a/sump2/impl/impl_syn.prj b/sump2/impl/impl_syn.prj
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+#-- Synopsys, Inc.\r
+#-- Project file C:\Users\shchen\Documents\shao\iCE_demo\to_ted\release\LED_rotation\impl\impl_syn.prj\r
+#project files\r
+\r
+add_file -verilog -lib work "../source/top.v" \r
+add_file -verilog -lib work "../source/core.v" \r
+add_file -verilog -lib work "../source/mesa2ctrl.v" \r
+add_file -verilog -lib work "../source/mesa2lb.v" \r
+add_file -verilog -lib work "../source/mesa_core.v" \r
+add_file -verilog -lib work "../source/mesa_decode.v" \r
+add_file -verilog -lib work "../source/spi_byte2bit.v" \r
+add_file -verilog -lib work "../source/spi_prom.v" \r
+add_file -verilog -lib work "../source/time_stamp.v" \r
+add_file -verilog -lib work "../source/mesa_phy.v" \r
+add_file -verilog -lib work "../source/mesa_uart.v" \r
+add_file -verilog -lib work "../source/mesa_tx_uart.v" \r
+add_file -verilog -lib work "../source/mesa_ascii2nibble.v" \r
+add_file -verilog -lib work "../source/mesa_byte2ascii.v" \r
+add_file -verilog -lib work "../source/sump2.v" \r
+add_file -verilog -lib work "../source/top_pll.v" \r
+add_file -constraint -lib work "../constraint/top.sdc"\r
+#implementation: "impl_Implmnt"\r
+impl -add impl_Implmnt -type fpga\r
+\r
+#implementation attributes\r
+set_option -vlog_std v2001\r
+set_option -project_relative_includes 1\r
+\r
+#device options\r
+set_option -technology SBTiCE40\r
+set_option -part iCE40HX1K\r
+set_option -package TQ144\r
+set_option -speed_grade \r
+set_option -part_companion ""\r
+\r
+#compilation/mapping options\r
+\r
+# mapper_options\r
+set_option -frequency auto\r
+set_option -write_verilog 0\r
+set_option -write_vhdl 0\r
+\r
+# Silicon Blue iCE40\r
+set_option -maxfan 10000\r
+set_option -disable_io_insertion 0\r
+set_option -pipe 1\r
+set_option -retiming 0\r
+set_option -update_models_cp 0\r
+set_option -fixgatedclocks 2\r
+set_option -fixgeneratedclocks 0\r
+\r
+# NFilter\r
+set_option -popfeed 0\r
+set_option -constprop 0\r
+set_option -createhierarchy 0\r
+\r
+# sequential_optimization_options\r
+set_option -symbolic_fsm_compiler 1\r
+\r
+# Compiler Options\r
+set_option -compiler_compatible 0\r
+set_option -resource_sharing 1\r
+\r
+#automatic place and route (vendor) options\r
+set_option -write_apr_constraint 1\r
+\r
+#set result format/file last\r
+project -result_format "edif"\r
+project -result_file ./impl_Implmnt/impl.edf\r
+impl -active impl_Implmnt\r
+project -run synthesis -clean\r