--- /dev/null
+/* ****************************************************************************\r
+-- Source file: core.v \r
+-- Date: October 15, 2016\r
+-- Author: khubbard\r
+-- Description: Core wrapper for the logic. Minimized for fit to HX1K fabric.\r
+-- Language: Verilog-2001 and VHDL-1993\r
+-- Simulation: Mentor-Modelsim \r
+-- Synthesis: Xilinst-XST \r
+-- License: This project is licensed with the CERN Open Hardware Licence\r
+-- v1.2. You may redistribute and modify this project under the\r
+-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+-- v.1.2 for applicable Conditions.\r
+--\r
+-- Revision History:\r
+-- Ver# When Who What\r
+-- ---- -------- -------- ---------------------------------------------------\r
+-- 0.1 10.15.16 khubbard Creation\r
+-- ***************************************************************************/\r
+`default_nettype none // Strictly enforce all nets to be declared\r
+\r
+module core \r
+(\r
+ input wire reset,\r
+ input wire clk_lb, \r
+ input wire clk_cap, \r
+ input wire lb_wr,\r
+ input wire lb_rd,\r
+ input wire [23:0] events_din,\r
+ input wire [31:0] lb_addr,\r
+ input wire [31:0] lb_wr_d,\r
+ output wire [31:0] lb_rd_d,\r
+ output wire lb_rd_rdy,\r
+ output wire [3:0] led_bus\r
+);// module core\r
+\r
+\r
+ wire [31:0] u0_lb_rd_d;\r
+ wire u0_lb_rd_rdy;\r
+ wire [31:0] user_ctrl;\r
+ wire lb_cs_sump2_ctrl;\r
+ wire lb_cs_sump2_data;\r
+//wire [31:0] time_stamp_d;\r
+//reg [31:0] lb_08_reg;\r
+//reg [15:0] test_cnt;\r
+//reg [9:0] h_cnt;\r
+//reg [9:0] v_cnt;\r
+//reg h_sync;\r
+//reg h_valid;\r
+//reg v_sync;\r
+\r
+\r
+// ----------------------------------------------------------------------------\r
+// Test Design. VGA Controller\r
+// 3 Build Choices that fit the HX1K\r
+// o 16 bits from the Pins\r
+// o 8 bits of pins or 8 test counter on user_ctrl[0] == 1\r
+// o Sample graphics controller design ( 3 signals ).\r
+// ----------------------------------------------------------------------------\r
+//always @ ( posedge clk_cap ) begin : proc_test_cnt\r
+// if ( user_ctrl[0] == 0 ) begin\r
+// test_cnt[15:0] <= events_din[15:0];\r
+// end else begin\r
+// test_cnt[7:0] <= test_cnt[7:0] + 1;\r
+// end \r
+// h_sync <= 0;\r
+// h_valid <= 0;\r
+// if ( h_cnt == 10'd800 ) begin\r
+// h_cnt <= 10'd1;\r
+// h_sync <= 1;\r
+// end else begin\r
+// h_valid <= 1;\r
+// h_cnt <= h_cnt + 1;\r
+// end \r
+// if ( h_sync == 1 ) begin\r
+// if ( v_cnt == 10'd600 ) begin\r
+// v_cnt <= 10'd1;\r
+// v_sync <= 1;\r
+// end else begin\r
+// v_sync <= 0;\r
+// v_cnt <= v_cnt + 1;\r
+// end \r
+// end\r
+//end\r
+\r
+\r
+// ----------------------------------------------------------------------------\r
+// LocalBus Test Registers \r
+// ----------------------------------------------------------------------------\r
+//always @ ( posedge clk_lb or posedge reset ) begin : proc_name\r
+// if ( reset == 1 ) begin\r
+// lb_rd_d <= 32'd0;\r
+// lb_rd_rdy <= 0;\r
+// lb_08_reg <= 32'd0;\r
+// end else begin\r
+// lb_rd_d <= 32'd0;\r
+// lb_rd_rdy <= 0;\r
+//\r
+// if ( lb_wr == 1 && lb_addr[19:16] == 4'H0 ) begin\r
+// if ( lb_addr[15:0] == 16'h0008 ) begin\r
+// lb_08_reg[31:0] <= lb_wr_d[31:0];\r
+// end\r
+// end // if ( lb_wr == 1 )\r
+//\r
+// if ( lb_rd == 1 && lb_addr[19:16] == 4'H0 ) begin\r
+// if ( lb_addr[15:0] == 16'h0000 ) begin\r
+// lb_rd_rdy <= 1;\r
+// lb_rd_d[31:0] <= 32'h12345678;\r
+// end\r
+// if ( lb_addr[15:0] == 16'h0004 ) begin\r
+// lb_rd_rdy <= 1;\r
+// lb_rd_d[31:0] <= time_stamp_d[31:0];\r
+// end\r
+// if ( lb_addr[15:0] == 16'h0008 ) begin\r
+// lb_rd_rdy <= 1;\r
+// lb_rd_d[31:0] <= lb_08_reg[31:0];\r
+// end \r
+// end // if ( lb_rd == 1 ) begin\r
+//\r
+// if ( u0_lb_rd_rdy == 1 ) begin\r
+// lb_rd_rdy <= 1;\r
+// lb_rd_d <= u0_lb_rd_d[31:0];\r
+// end\r
+// end // clk+reset\r
+//end // proc_name\r
+\r
+//assign lb_cs_sump2_ctrl = ( lb_addr[3:0] == 4'h0 ) ? 1 : 0;\r
+//assign lb_cs_sump2_data = ( lb_addr[3:0] == 4'h4 ) ? 1 : 0;\r
+ assign lb_cs_sump2_ctrl = ~ lb_addr[2];// 0x0\r
+ assign lb_cs_sump2_data = lb_addr[2];// 0x4\r
+\r
+ assign lb_rd_rdy = u0_lb_rd_rdy;\r
+ assign lb_rd_d = u0_lb_rd_d[31:0];\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// 32bit UNIX TimeStamp of when the design was synthesized\r
+//-----------------------------------------------------------------------------\r
+//time_stamp u_time_stamp\r
+//(\r
+// .time_dout ( time_stamp_d )\r
+//);\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// SUMP2 Example\r
+//-----------------------------------------------------------------------------\r
+sump2\r
+#\r
+(\r
+ .depth_len ( 1024 ),\r
+ .depth_bits ( 10 ),\r
+ .event_bytes ( 2 ),\r
+ .data_dwords ( 0 ),\r
+ .nonrle_en ( 0 ),\r
+ .rle_en ( 1 ),\r
+ .pattern_en ( 0 ),\r
+ .trigger_nth_en ( 0 ),\r
+ .trigger_dly_en ( 0 ),\r
+ .trigger_wd_en ( 0 ),\r
+ .freq_mhz ( 16'd96 ),\r
+ .freq_fracts ( 16'h0000 )\r
+)\r
+u_sump2\r
+(\r
+ .reset ( reset ),\r
+ .clk_lb ( clk_lb ),\r
+ .clk_cap ( clk_cap ),\r
+ .lb_cs_ctrl ( lb_cs_sump2_ctrl ),\r
+ .lb_cs_data ( lb_cs_sump2_data ),\r
+ .lb_wr ( lb_wr ),\r
+ .lb_rd ( lb_rd ),\r
+ .lb_wr_d ( lb_wr_d[31:0] ),\r
+ .lb_rd_d ( u0_lb_rd_d ),\r
+ .lb_rd_rdy ( u0_lb_rd_rdy ),\r
+ .active ( ),\r
+ .trigger_in ( 1'b0 ),\r
+ .trigger_out ( ),\r
+ .events_din ( {16'd0,events_din[15:0]} ),\r
+ .dwords_3_0 ( 128'd0 ),\r
+ .dwords_7_4 ( 128'd0 ),\r
+ .dwords_11_8 ( 128'd0 ),\r
+ .dwords_15_12 ( 128'd0 ),\r
+ .led_bus ( led_bus[3:0] ),\r
+ .user_ctrl ( user_ctrl[31:0] ),\r
+ .user_pat0 ( ),\r
+ .user_pat1 ( )\r
+);\r
+\r
+\r
+endmodule // core\r
projects / BML_sump2 / blobdiff