--- /dev/null
+/* ****************************************************************************\r
+-- (C) Copyright 2015 Kevin M. Hubbard @ Black Mesa Labs\r
+-- Source file: mesa2ctrl.v \r
+-- Date: October 4, 2015 \r
+-- Author: khubbard\r
+-- Language: Verilog-2001 \r
+-- Description: The Mesa Bus to Control Bus translator. Decodes all subslot \r
+-- command nibbles for this slot. Write Only Operations.\r
+-- License: This project is licensed with the CERN Open Hardware Licence\r
+-- v1.2. You may redistribute and modify this project under the\r
+-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+-- v.1.2 for applicable Conditions.\r
+--\r
+-- "\n"..."FFFF"."(F0-12-34-04)[11223344]\n" : \r
+-- 0xFF = Bus Idle ( NULLs )\r
+-- B0 0xF0 = New Bus Cycle to begin ( Nibble and bit orientation )\r
+-- B1 0x12 = Slot Number, 0xFF = Broadcast all slots, 0xFE = NULL Dest\r
+-- B2 0x3 = Sub-Slot within the chip (0-0xF)\r
+-- 0x4 = Command Nibble for Sub-Slot\r
+-- B3 0x04 = Number of Payload Bytes (0-255)\r
+-- 0x11223344 = Payload\r
+--\r
+-- Slot 0xFF = Broadcast all slots\r
+-- Sub-Slot 0x0 = User Local Bus Access\r
+-- Sub-Slot 0xE = PROM Local Bus Access\r
+-- 0x0 = Bus Write\r
+-- 0x1 = Bus Read\r
+-- 0x2 = Bus Write Repeat ( burst to single address )\r
+-- 0x3 = Bus Read Repeat ( burst read from single address )\r
+-- Sub-Slot 0xF = Power and Pin Control ( Write Only )\r
+-- \r
+-- Revision History:\r
+-- Ver# When Who What\r
+-- ---- -------- -------- ---------------------------------------------------\r
+-- 0.1 10.04.15 khubbard Creation\r
+-- ***************************************************************************/\r
+`default_nettype none // Strictly enforce all nets to be declared\r
+ \r
+module mesa2ctrl\r
+(\r
+ input wire clk,\r
+ input wire reset,\r
+ input wire rx_byte_start,\r
+ input wire rx_byte_stop,\r
+ input wire rx_byte_rdy,\r
+ input wire [7:0] rx_byte_d,\r
+ output reg [8:0] subslot_ctrl\r
+); // module mesa2ctrl\r
+\r
+ reg [3:0] byte_cnt;\r
+ reg [31:0] dword_sr;\r
+ reg rx_byte_rdy_p1;\r
+ reg rx_byte_rdy_p2;\r
+ reg rx_byte_rdy_p3;\r
+ reg rx_byte_stop_p1;\r
+ reg rx_byte_stop_p2;\r
+ reg rx_byte_stop_p3;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Shift a nibble into a byte shift register. \r
+// |---- Header ----|--- Payload ---|\r
+// 0 1 2 3\r
+// Write : <F0><00><00><08>[<ADDR><DATA>]\r
+// Read : <F0><00><00><08>[<ADDR><Length>]\r
+//-----------------------------------------------------------------------------\r
+always @ ( posedge clk ) begin : proc_lb1\r
+ rx_byte_rdy_p1 <= rx_byte_rdy;\r
+ rx_byte_rdy_p2 <= rx_byte_rdy_p1;\r
+ rx_byte_rdy_p3 <= rx_byte_rdy_p2;\r
+ rx_byte_stop_p1 <= rx_byte_stop;\r
+ rx_byte_stop_p2 <= rx_byte_stop_p1;\r
+ rx_byte_stop_p3 <= rx_byte_stop_p2;\r
+\r
+ if ( rx_byte_start == 1 ) begin\r
+ byte_cnt <= 4'd0;\r
+ end else if ( rx_byte_rdy == 1 ) begin \r
+ if ( byte_cnt != 4'd4 ) begin\r
+ byte_cnt <= byte_cnt + 1; \r
+ end\r
+ end \r
+\r
+ // Shift bytes into a 32bit SR\r
+ if ( rx_byte_rdy == 1 ) begin \r
+ dword_sr[31:0] <= { dword_sr[23:0], rx_byte_d[7:0] };\r
+ end\r
+\r
+ subslot_ctrl[8] <= 0;// Strobe \r
+ // Accept single DWORD packets for Slot-00 (this) or Slot-FF (all)\r
+ if ( rx_byte_rdy_p2 == 1 && byte_cnt[3:0] == 4'd3 ) begin\r
+ if ( dword_sr[31:16] == 16'hF000 || \r
+ dword_sr[31:16] == 16'hF0FF ) begin\r
+ // Payload must be 0x00 length\r
+ if ( dword_sr[7:0] == 8'h00 ) begin\r
+ subslot_ctrl <= { 1'b1, dword_sr[15:8] };// D(8) is Strobe\r
+ end\r
+ end\r
+ end\r
+\r
+ if ( reset == 1 ) begin\r
+ byte_cnt <= 4'd0;\r
+ end\r
+ \r
+end // proc_lb1\r
+\r
+\r
+endmodule // mesa2ctrl\r
projects / BML_sump2 / blobdiff