--- /dev/null
+/* ****************************************************************************\r
+-- Source file: mesa_phy.v \r
+-- Date: October 2015 \r
+-- Author: khubbard\r
+-- Description: Interface the Byte binary stream of the internal Mesa-Bus with\r
+-- the physical layer. For this case, using UARTs.\r
+-- This instantiates the UARTs and takes care of the binary to\r
+-- ASCII conversions for all directions.\r
+-- Language: Verilog-2001 and VHDL-1993\r
+-- Simulation: Mentor-Modelsim \r
+-- Synthesis: Lattice \r
+-- License: This project is licensed with the CERN Open Hardware Licence\r
+-- v1.2. You may redistribute and modify this project under the\r
+-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+-- v.1.2 for applicable Conditions.\r
+--\r
+-- Revision History:\r
+-- Ver# When Who What\r
+-- ---- -------- -------- ---------------------------------------------------\r
+-- 0.1 10.04.15 khubbard Creation\r
+-- ***************************************************************************/\r
+`default_nettype none // Strictly enforce all nets to be declared\r
+\r
+module mesa_phy\r
+(\r
+ input wire clk,\r
+ input wire reset,\r
+ input wire disable_chain,\r
+ input wire clr_baudlock,\r
+ output wire mesa_wi_baudlock,\r
+\r
+ input wire mesa_wi,\r
+ output wire mesa_wo,\r
+ input wire mesa_ri,\r
+ output wire mesa_ro,\r
+\r
+ output wire mesa_wi_nib_en,\r
+ output wire [3:0] mesa_wi_nib_d,\r
+ input wire mesa_wo_byte_en,\r
+ input wire [7:0] mesa_wo_byte_d,\r
+ output wire mesa_wo_busy, \r
+ input wire mesa_ro_byte_en,\r
+ input wire [7:0] mesa_ro_byte_d,\r
+ output wire mesa_ro_busy,\r
+ input wire mesa_ro_done \r
+);// module mesa_phy\r
+\r
+\r
+ wire wi_char_en;\r
+ wire [7:0] wi_char_d;\r
+ wire ro_char_en;\r
+ wire [7:0] ro_char_d;\r
+ wire ro_uart_busy;\r
+ wire ro_uart_idle;\r
+ wire wo_char_en;\r
+ wire [7:0] wo_char_d;\r
+ wire wo_uart_busy;\r
+ wire baud_lock;\r
+ wire [15:0] baud_rate;\r
+\r
+ assign mesa_wi_baudlock = baud_lock;\r
+\r
+//-----------------------------------------------------------------------------\r
+// UART to convert serial streams to/from ASCII bytes for Wi and Ro.\r
+//-----------------------------------------------------------------------------\r
+mesa_uart u_mesa_uart\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset ),\r
+ .clr_baudlock ( clr_baudlock ),\r
+ .en_autobaud ( 1'b1 ),\r
+//.en_autobaud ( 1'b0 ),\r
+ .rxd ( mesa_wi ),\r
+ .txd ( mesa_ro ),\r
+ .flush ( ),\r
+ .dbg ( ),\r
+ .rx_rdy ( wi_char_en ),\r
+ .rx_byte ( wi_char_d[7:0] ),\r
+\r
+ .tx_en ( ro_char_en ),\r
+ .tx_byte ( ro_char_d[7:0] ),\r
+ .tx_busy ( ro_uart_busy ),\r
+ .tx_idle ( ro_uart_idle ),\r
+ .rx_idle ( ),\r
+ .baud_rate ( baud_rate[15:0] ),\r
+ .baud_lock ( baud_lock )\r
+); // module mesa_uart\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// TX Only UART. Sends Wo data. When 1st UART goes to lock, sends "\n" out, \r
+// otherwise just echos the binary stream from decode block ( Wi->Wo ).\r
+//-----------------------------------------------------------------------------\r
+mesa_tx_uart u_mesa_tx_uart\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset | disable_chain ),\r
+ .txd ( mesa_wo ),\r
+ .tx_en ( wo_char_en ),\r
+ .tx_byte ( wo_char_d[7:0] ),\r
+ .tx_busy ( wo_uart_busy ),\r
+ .baud_rate ( baud_rate[15:0] ),\r
+ .baud_lock ( baud_lock )\r
+); // module mesa_uart\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Convert Wi ASCII to Binary Nibbles. Decoder figures out nibble/byte phase\r
+//-----------------------------------------------------------------------------\r
+mesa_ascii2nibble u_mesa_ascii2nibble\r
+(\r
+ .clk ( clk ),\r
+ .rx_char_en ( wi_char_en ),\r
+ .rx_char_d ( wi_char_d[7:0] ),\r
+ .rx_nib_en ( mesa_wi_nib_en ),\r
+ .rx_nib_d ( mesa_wi_nib_d[3:0] )\r
+);// module mesa_ascii2nibble\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Convert Ro Binary Bytes to ASCII \r
+//-----------------------------------------------------------------------------\r
+mesa_byte2ascii u0_mesa_byte2ascii\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset ),\r
+ .tx_byte_en ( mesa_ro_byte_en ),\r
+ .tx_byte_d ( mesa_ro_byte_d[7:0] ),\r
+ .tx_byte_busy ( mesa_ro_busy ),\r
+ .tx_byte_done ( mesa_ro_done ),\r
+ .tx_char_en ( ro_char_en ),\r
+ .tx_char_d ( ro_char_d[7:0] ),\r
+ .tx_char_busy ( ro_uart_busy ),\r
+ .tx_char_idle ( ro_uart_idle ) \r
+);// module mesa_byte2ascii\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Convert Wo Binary Bytes to ASCII \r
+//-----------------------------------------------------------------------------\r
+mesa_byte2ascii u1_mesa_byte2ascii\r
+(\r
+ .clk ( clk ),\r
+ .reset ( reset | disable_chain ),\r
+ .tx_byte_en ( mesa_wo_byte_en ),\r
+ .tx_byte_d ( mesa_wo_byte_d[7:0] ),\r
+ .tx_byte_busy ( mesa_wo_busy ),\r
+ .tx_byte_done ( 1'b0 ),\r
+ .tx_char_en ( wo_char_en ),\r
+ .tx_char_d ( wo_char_d[7:0] ),\r
+ .tx_char_busy ( wo_uart_busy ) \r
+);// module mesa_byte2ascii\r
+\r
+\r
+endmodule // mesa_phy.v\r
projects / BML_sump2 / blobdiff