https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/

[BML_sump2] / sump2 / source / mesa_tx_uart.v

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+/* ****************************************************************************\r
+-- (C) Copyright 2015 Black Mesa Labs\r
+-- Source file: mesa_tx_uart.v                \r
+-- Date:        June 1, 2015   \r
+-- Author:      khubbard\r
+-- Description: TX only 1/2 of UART for transmitting Wo bytes.\r
+-- Language:    Verilog-2001 \r
+-- License:     This project is licensed with the CERN Open Hardware Licence\r
+--              v1.2.  You may redistribute and modify this project under the\r
+--              terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+--              This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+--              WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+--              AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+--              v.1.2 for applicable Conditions.\r
+--\r
+-- RXD    \START/<D0><D1><D2><..><D7>/STOP\r
+-- Design Statistics after Packing\r
+-- en_clr_lock = 1;\r
+--    Number of LUTs  : 190 / 384\r
+--    Number of DFFs  : 110 / 384\r
+--\r
+-- Revision History:\r
+-- Ver#  When      Who      What\r
+-- ----  --------  -------- ---------------------------------------------------\r
+-- 0.1   06.01.15  khubbard Creation\r
+-- ***************************************************************************/\r
+//`default_nettype none // Strictly enforce all nets to be declared\r
+                                                                                \r
+module mesa_tx_uart\r
+(\r
+  input  wire         reset,\r
+  input  wire         clk,\r
+  input  wire [7:0]   tx_byte,\r
+  input  wire         tx_en,\r
+  output reg          tx_busy,\r
+  output reg          txd,\r
+  input  wire         baud_lock,\r
+  input  wire [15:0]  baud_rate\r
+); // module mesa_tx_uart\r
+\r
+\r
+  reg  [15:0]   tx_cnt_16b;\r
+  reg  [3:0]    tx_bit_cnt;\r
+  reg  [9:0]    tx_sr;\r
+  reg           txd_loc;\r
+  reg           tx_shift;\r
+  reg           tx_now;\r
+  reg           tx_en_p1;\r
+  reg           baud_lock_p1;\r
+  reg           send_lf;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// TX : Load 8bits into 10bit SR and shift out at the RX baud rate    \r
+//-----------------------------------------------------------------------------\r
+always @ ( posedge clk ) begin : proc_tx \r
+ begin\r
+  tx_shift     <= 0;\r
+  tx_busy      <= 0;\r
+  txd          <= txd_loc;\r
+  txd_loc      <= tx_sr[0];\r
+  tx_now       <= 0;\r
+  tx_en_p1     <= tx_en;\r
+  baud_lock_p1 <= baud_lock;   \r
+  send_lf      <= baud_lock & ~ baud_lock_p1;\r
+\r
+  // Load a new Byte to send\r
+  if ( ( tx_en == 1 && tx_en_p1 == 0 ) || ( send_lf == 1 )  ) begin\r
+    tx_bit_cnt <= 4'd10;\r
+    tx_cnt_16b <= 16'h0000;\r
+    tx_busy    <= 1;\r
+    tx_shift   <= 1;\r
+    tx_sr[9:0] <= { 1'b1, tx_byte[7:0], 1'b0 };\r
+    if ( send_lf == 1 ) begin\r
+      tx_sr[9:0] <= { 1'b1, 8'h0A , 1'b0 };// Used for autobauding next node\r
+    end \r
+\r
+  // Shift and send the byte until bit_cnt goes to 0\r
+  end else if ( tx_bit_cnt != 4'd0 ) begin\r
+    tx_cnt_16b <= tx_cnt_16b + 1;\r
+    tx_busy    <= 1;\r
+    if ( tx_now == 1 ) begin\r
+      tx_shift   <= 1;\r
+      tx_bit_cnt <= tx_bit_cnt[3:0] - 1;\r
+      tx_cnt_16b <= 16'h0000;\r
+      tx_sr[9:0] <= { 1'b1, tx_sr[9:1] };\r
+    end\r
+  end else begin\r
+    tx_sr <= 10'H3FF;\r
+  end\r
+\r
+  if ( tx_cnt_16b[15:0] == baud_rate[15:0] ) begin\r
+    tx_now <= 1;\r
+  end\r
+\r
+  if ( reset == 1 ) begin\r
+    tx_bit_cnt <= 4'd0;\r
+  end\r
+\r
+ end\r
+end // proc_tx\r
+\r
+\r
+endmodule // mesa_tx_uart\r