--- /dev/null
+/* ****************************************************************************\r
+-- Source file: top.v \r
+-- Date: October 08, 2016\r
+-- Author: khubbard\r
+-- Description: Top Level Verilog RTL for Lattice ICE5LP FPGA Design\r
+-- Language: Verilog-2001 and VHDL-1993\r
+-- Simulation: Mentor-Modelsim \r
+-- Synthesis: Lattice \r
+-- License: This project is licensed with the CERN Open Hardware Licence\r
+-- v1.2. You may redistribute and modify this project under the\r
+-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).\r
+-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED\r
+-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY\r
+-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL\r
+-- v.1.2 for applicable Conditions.\r
+-- \r
+-- Lattice ICE-Stick\r
+-- -----------------------------------------------------------\r
+-- / 119 118 117 116 115 114 113 112 GND 3V |\r
+-- / o o o o o o o o o o |\r
+-- / ----- |\r
+-- ------- --------- R 3V |o o|3V |\r
+-- | ------- | | | GND |o P o|GND |\r
+-- |USB | FTDI | |Lattice | R--G--R event[7]|o M o|event[6] |\r
+-- | |FT2232H| |iCE40HX1K| | event[5]|o O o|event[4] |\r
+-- | ------- | | R event[3]|o D o|event[2] |\r
+-- ------- --------- event[1]|o o|event[0] |\r
+-- \ ----- |\r
+-- \ o o o o o o o o o o |\r
+-- \ 44 45 47 48 56 60 61 62 GND 3V |\r
+-- ----------------------------------------------------------- \r
+-- event [15][14][13][12][11][10] [9] [8]\r
+--\r
+-- Revision History:\r
+-- Ver# When Who What\r
+-- ---- -------- -------- ---------------------------------------------------\r
+-- 0.1 10.08.16 khubbard Creation\r
+-- ***************************************************************************/\r
+`default_nettype none // Strictly enforce all nets to be declared\r
+\r
+module top\r
+(\r
+ input wire clk_12m,\r
+ input wire ftdi_wi,\r
+ output wire ftdi_ro,\r
+ input wire [7:0] events_din,\r
+\r
+ input wire p44,\r
+ input wire p45,\r
+ input wire p47,\r
+ input wire p48,\r
+ input wire p56,\r
+ input wire p60,\r
+ input wire p61,\r
+ input wire p62,\r
+\r
+ output wire p119, \r
+ output wire p118, \r
+ output wire p117, \r
+ output wire p116, \r
+ output wire p115, \r
+ output wire p114, \r
+ output wire p113, \r
+ output wire p112, \r
+\r
+ input wire p128, \r
+\r
+ output wire spi_sck,\r
+ output wire spi_cs_l,\r
+ output wire spi_mosi,\r
+ input wire spi_miso,\r
+\r
+ output wire ir_sd,\r
+ output wire ir_txd,\r
+ input wire ir_rxd,\r
+\r
+ output wire LED1,\r
+ output wire LED2,\r
+ output wire LED3,\r
+ output wire LED4,\r
+ output wire LED5\r
+);// module top\r
+\r
+ wire lb_wr;\r
+ wire lb_rd;\r
+ wire [31:0] lb_addr;\r
+ wire [31:0] lb_wr_d;\r
+ wire [31:0] lb_rd_d;\r
+ wire lb_rd_rdy;\r
+ wire [23:0] events_loc;\r
+\r
+ wire clk_96m_loc;\r
+ wire clk_cap_tree;\r
+ wire clk_lb_tree;\r
+//wire reset_core;\r
+ wire reset_loc;\r
+ wire pll_lock;\r
+\r
+ wire mesa_wi_loc;\r
+ wire mesa_wo_loc;\r
+ wire mesa_ri_loc;\r
+ wire mesa_ro_loc;\r
+\r
+ wire mesa_wi_nib_en;\r
+ wire [3:0] mesa_wi_nib_d;\r
+ wire mesa_wo_byte_en;\r
+ wire [7:0] mesa_wo_byte_d;\r
+ wire mesa_wo_busy;\r
+ wire mesa_ro_byte_en;\r
+ wire [7:0] mesa_ro_byte_d;\r
+ wire mesa_ro_busy;\r
+ wire mesa_ro_done;\r
+ wire [7:0] mesa_core_ro_byte_d;\r
+ wire mesa_core_ro_byte_en;\r
+ wire mesa_core_ro_done;\r
+ wire mesa_core_ro_busy;\r
+\r
+\r
+ wire mesa_wi_baudlock;\r
+ wire [3:0] led_bus;\r
+ reg [7:0] test_cnt;\r
+ reg ck_togl;\r
+\r
+ assign LED1 = led_bus[0];\r
+ assign LED2 = led_bus[1];\r
+ assign LED3 = led_bus[2];\r
+ assign LED4 = led_bus[3];\r
+ assign LED5 = 1'b1;// Green LED always ON. Not enough resources to flash\r
+\r
+ assign ir_sd = 1'b1;// 1==Shutdown 0==ON\r
+ assign ir_txd = 1'b0;\r
+\r
+ assign reset_loc = 0;\r
+//assign reset_core = ~ pll_lock;// didn't fit\r
+\r
+ // Hookup FTDI RX and TX pins to MesaBus Phy\r
+ assign mesa_wi_loc = ftdi_wi;\r
+ assign ftdi_ro = mesa_ro_loc;\r
+\r
+\r
+ assign events_loc[7:0] = events_din[7:0];\r
+ assign events_loc[15:8] = { p44,p45,p47,p48,p56,p60,p61,p62 };\r
+//assign events_loc[23:16] = { p119,p118,p117,p116,p115,p114,p113,p112 };\r
+ assign events_loc[23:16] = 8'd0;// Didn't fit\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// PLL generated by Lattice GUI to multiply 12 MHz to 96 MHz\r
+// PLL's RESET port is active low. How messed up of a signal name is that?\r
+//-----------------------------------------------------------------------------\r
+top_pll u_top_pll\r
+(\r
+ .REFERENCECLK ( clk_12m ),\r
+ .PLLOUTCORE ( ),\r
+ .PLLOUTGLOBAL ( clk_96m_loc ),\r
+ .LOCK ( pll_lock ),\r
+ .RESET ( 1'b1 )\r
+);\r
+\r
+\r
+SB_GB u0_sb_gb \r
+(\r
+//.USER_SIGNAL_TO_GLOBAL_BUFFER ( clk_12m ),\r
+ .USER_SIGNAL_TO_GLOBAL_BUFFER ( ck_togl ),\r
+//.USER_SIGNAL_TO_GLOBAL_BUFFER ( clk_96m_loc ),\r
+ .GLOBAL_BUFFER_OUTPUT ( clk_lb_tree )\r
+);\r
+// Note: sump2.v modified to conserve resources requires single clock domain\r
+//assign clk_cap_tree = clk_lb_tree;\r
+\r
+SB_GB u1_sb_gb \r
+(\r
+//.USER_SIGNAL_TO_GLOBAL_BUFFER ( ck_cap_togl ),\r
+ .USER_SIGNAL_TO_GLOBAL_BUFFER ( clk_96m_loc ),\r
+ .GLOBAL_BUFFER_OUTPUT ( clk_cap_tree )\r
+);\r
+// assign clk_lb_tree = clk_12m;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Note: 40kHz modulated ir_rxd signal looks like this\r
+// \_____/ \___/ \___/\r
+// |<2us>|<-------24us----------->\r
+//-----------------------------------------------------------------------------\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Toggle Flop To generate slower capture clocks.\r
+// 12MHz div-6 = 1 MHz toggle 1uS Sample\r
+// 12MHz div-48 = 125 kHz toggle 8uS Sample\r
+//-----------------------------------------------------------------------------\r
+//always @ ( posedge clk_12m ) begin : proc_div\r
+always @ ( posedge clk_cap_tree ) begin : proc_div\r
+ begin\r
+ test_cnt <= test_cnt[7:0] + 1;\r
+// ck_togl <= ~ ck_togl;// 48 MHz\r
+ ck_togl <= test_cnt[1];// 24 MHz\r
+ end\r
+end // proc_div\r
+//assign p119 = test_cnt[7];\r
+//assign p118 = test_cnt[6];\r
+//assign p117 = test_cnt[5];\r
+//assign p116 = test_cnt[4];\r
+//assign p115 = test_cnt[3];\r
+//assign p114 = test_cnt[2];\r
+//assign p113 = test_cnt[1];\r
+//assign p112 = test_cnt[0];\r
+ \r
+ assign p119 = test_cnt[5];\r
+ assign p118 = test_cnt[4];\r
+ assign p117 = test_cnt[3];\r
+ assign p116 = test_cnt[2];\r
+ assign p115 = test_cnt[1];\r
+ assign p114 = test_cnt[0];\r
+//assign p116 = lb_rd_rdy;\r
+//assign p115 = lb_rd;\r
+//assign p114 = lb_wr;\r
+\r
+//assign p119 = 1'b0;\r
+//assign p118 = 1'b0;\r
+//assign p117 = 1'b0;\r
+//assign p116 = 1'b0;\r
+//assign p115 = 1'b0;\r
+//assign p114 = 1'b0;\r
+ assign p113 = mesa_ro_loc;\r
+ assign p112 = ftdi_wi;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// FSM for reporting ID : This also muxes in Ro Byte path from Core\r
+// This didn't fit in ICE-Stick, so removed.\r
+//-----------------------------------------------------------------------------\r
+//mesa_id u_mesa_id\r
+//(\r
+// .reset ( reset_loc ),\r
+// .clk ( clk_lb_tree ),\r
+// .report_id ( report_id ),\r
+// .id_mfr ( 32'h00000001 ),\r
+// .id_dev ( 32'h00000002 ),\r
+// .id_snum ( 32'h00000001 ),\r
+//\r
+// .mesa_core_ro_byte_en ( mesa_core_ro_byte_en ),\r
+// .mesa_core_ro_byte_d ( mesa_core_ro_byte_d[7:0] ),\r
+// .mesa_core_ro_done ( mesa_core_ro_done ),\r
+// .mesa_ro_byte_en ( mesa_ro_byte_en ),\r
+// .mesa_ro_byte_d ( mesa_ro_byte_d[7:0] ),\r
+// .mesa_ro_done ( mesa_ro_done ),\r
+// .mesa_ro_busy ( mesa_ro_busy )\r
+//);// module mesa_id\r
+ assign mesa_ro_byte_d[7:0] = mesa_core_ro_byte_d[7:0];\r
+ assign mesa_ro_byte_en = mesa_core_ro_byte_en;\r
+ assign mesa_ro_done = mesa_core_ro_done;\r
+ assign mesa_core_ro_busy = mesa_ro_busy;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// MesaBus Phy : Convert UART serial to/from binary for Mesa Bus Interface\r
+// This translates between bits and bytes\r
+//-----------------------------------------------------------------------------\r
+mesa_phy u_mesa_phy\r
+(\r
+//.reset ( reset_core ),\r
+ .reset ( reset_loc ),\r
+ .clk ( clk_lb_tree ),\r
+ .clr_baudlock ( 1'b0 ),\r
+ .disable_chain ( 1'b1 ),\r
+ .mesa_wi_baudlock ( mesa_wi_baudlock ),\r
+ .mesa_wi ( mesa_wi_loc ),\r
+ .mesa_ro ( mesa_ro_loc ),\r
+ .mesa_wo ( mesa_wo_loc ),\r
+ .mesa_ri ( mesa_ri_loc ),\r
+ .mesa_wi_nib_en ( mesa_wi_nib_en ),\r
+ .mesa_wi_nib_d ( mesa_wi_nib_d[3:0] ),\r
+ .mesa_wo_byte_en ( mesa_wo_byte_en ),\r
+ .mesa_wo_byte_d ( mesa_wo_byte_d[7:0] ),\r
+ .mesa_wo_busy ( mesa_wo_busy ),\r
+ .mesa_ro_byte_en ( mesa_ro_byte_en ),\r
+ .mesa_ro_byte_d ( mesa_ro_byte_d[7:0] ),\r
+ .mesa_ro_busy ( mesa_ro_busy ),\r
+ .mesa_ro_done ( mesa_ro_done )\r
+);// module mesa_phy\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// MesaBus Core : Decode Slot,Subslot,Command Info and translate to LocalBus\r
+//-----------------------------------------------------------------------------\r
+mesa_core \r
+#\r
+(\r
+ .spi_prom_en ( 1'b0 )\r
+)\r
+u_mesa_core\r
+(\r
+//.reset ( reset_core ),\r
+ .reset ( ~mesa_wi_baudlock ),\r
+ .clk ( clk_lb_tree ),\r
+ .spi_sck ( spi_sck ),\r
+ .spi_cs_l ( spi_cs_l ),\r
+ .spi_mosi ( spi_mosi ),\r
+ .spi_miso ( spi_miso ),\r
+ .rx_in_d ( mesa_wi_nib_d[3:0] ),\r
+ .rx_in_rdy ( mesa_wi_nib_en ),\r
+ .tx_byte_d ( mesa_core_ro_byte_d[7:0] ),\r
+ .tx_byte_rdy ( mesa_core_ro_byte_en ),\r
+ .tx_done ( mesa_core_ro_done ),\r
+ .tx_busy ( mesa_core_ro_busy ),\r
+ .tx_wo_byte ( mesa_wo_byte_d[7:0] ),\r
+ .tx_wo_rdy ( mesa_wo_byte_en ),\r
+ .subslot_ctrl ( ),\r
+ .bist_req ( ),\r
+ .reconfig_req ( ),\r
+ .reconfig_addr ( ),\r
+ .oob_en ( 1'b0 ),\r
+ .oob_done ( 1'b0 ),\r
+ .lb_wr ( lb_wr ),\r
+ .lb_rd ( lb_rd ),\r
+ .lb_wr_d ( lb_wr_d[31:0] ),\r
+ .lb_addr ( lb_addr[31:0] ),\r
+ .lb_rd_d ( lb_rd_d[31:0] ),\r
+ .lb_rd_rdy ( lb_rd_rdy )\r
+);// module mesa_core\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Design Specific Logic\r
+//-----------------------------------------------------------------------------\r
+core u_core \r
+(\r
+//.reset ( reset_core ),\r
+ .reset ( ~mesa_wi_baudlock ),\r
+ .clk_lb ( clk_lb_tree ),\r
+ .clk_cap ( clk_cap_tree ),\r
+ .lb_wr ( lb_wr ),\r
+ .lb_rd ( lb_rd ),\r
+ .lb_wr_d ( lb_wr_d[31:0] ),\r
+ .lb_addr ( lb_addr[31:0] ),\r
+ .lb_rd_d ( lb_rd_d[31:0] ),\r
+ .lb_rd_rdy ( lb_rd_rdy ),\r
+ .led_bus ( led_bus[3:0] ),\r
+ .events_din ( events_loc[23:0] )\r
+); \r
+\r
+\r
+endmodule // top.v\r
projects / BML_sump2 / blobdiff