https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/

[BML_sump2] / sump2 / source / top_pll.v

diff --git a/sump2/source/top_pll.v b/sump2/source/top_pll.v
new file mode 100755 (executable)
index 0000000..efb12ea
--- /dev/null
+++ b/sump2/source/top_pll.v
@@ -0,0 +1,40 @@
+module top_pll(REFERENCECLK,\r
+               PLLOUTCORE,\r
+               PLLOUTGLOBAL,\r
+               RESET,\r
+               LOCK);\r
+\r
+input REFERENCECLK;\r
+input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ \r
+output PLLOUTCORE;\r
+output PLLOUTGLOBAL;\r
+output LOCK;\r
+\r
+SB_PLL40_CORE top_pll_inst(.REFERENCECLK(REFERENCECLK),\r
+                           .PLLOUTCORE(PLLOUTCORE),\r
+                           .PLLOUTGLOBAL(PLLOUTGLOBAL),\r
+                           .EXTFEEDBACK(),\r
+                           .DYNAMICDELAY(),\r
+                           .RESETB(RESET),\r
+                           .BYPASS(1'b0),\r
+                           .LATCHINPUTVALUE(),\r
+                           .LOCK(LOCK),\r
+                           .SDI(),\r
+                           .SDO(),\r
+                           .SCLK());\r
+\r
+//\\ Fin=12, Fout=96;\r
+defparam top_pll_inst.DIVR = 4'b0000;\r
+defparam top_pll_inst.DIVF = 7'b0111111;\r
+defparam top_pll_inst.DIVQ = 3'b011;\r
+defparam top_pll_inst.FILTER_RANGE = 3'b001;\r
+defparam top_pll_inst.FEEDBACK_PATH = "SIMPLE";\r
+defparam top_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";\r
+defparam top_pll_inst.FDA_FEEDBACK = 4'b0000;\r
+defparam top_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";\r
+defparam top_pll_inst.FDA_RELATIVE = 4'b0000;\r
+defparam top_pll_inst.SHIFTREG_DIV_MODE = 2'b00;\r
+defparam top_pll_inst.PLLOUT_SELECT = "GENCLK";\r
+defparam top_pll_inst.ENABLE_ICEGATE = 1'b0;\r
+\r
+endmodule\r