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+SUMP2 FAQ\r
+\r
+o Do I need to know about designing FPGAs to use SUMP2?\r
+ No. BML provides a pre-built "bit file" for running SUMP2 on an iCEstick.\r
+ You only need to be able to download the programming tool and follow the\r
+ instructions on loading the bit file into the FPGA's PROM.\r
+\r
+o How is this project related / affiliated to sump.org?\r
+ This project is not affiliated with sump.org, but was inspired greatly by\r
+ the original 2007 sump design for the $99 Spartan3 eval board.\r
+ The very 1st sump design by BML in 2014 ( "SUMP1-RLE" ) maintained protocol\r
+ compatibility allowing the BML hardware design to work with the sump.org Java\r
+ software. The "SUMP1-RLE" design was later enhanced in hardware requiring all\r
+ new software and all compatibility with the sump.org project was abandoned.\r
+ The 2016 "SUMP2" design is a complete do-over of lessons learned from SUMP1\r
+ both in hardware and software. The SUMP2 design scales to be both much bigger\r
+ and smaller simultaneously targetting $1000 FPGAs with 512+32 bits of capture\r
+ on down to 16 bits of capture for the $5 FPGA on the Lattice iCEstick board.\r
+\r
+o How does SUMP2 compare against a Saleae Logic-8 Logic Analyzer? \r
+ SUMP2 and Saleae Logic-8 overlap slightly in that they sample digital signals\r
+ using a PC. SUMP2 ( the Verilog ) is primarily an FPGA internal node analyzer\r
+ for capturing up to 544 internal nodes of an FPGA. The small iCEstick instance\r
+ of SUMP2 captures 16 external signals at 96 MSPS, which is somewhat comparable\r
+ to the Saleae Logic-8 that captures 8 external signals at 100 MSPS. The major\r
+ differences are that SUMP2 stores compressed RLE samples to an internal SRAM\r
+ versus the Saleae which streams samples to CPU DRAM offering an almost unlimited\r
+ capture depth ( seconds of capture versus milliseconds ). The Saleae software\r
+ is much more advanced, offering serial protocol analyzers and compiled C++ \r
+ efficiency. SUMP2 is more about capturing low level activity in an open-source\r
+ software and hardware environment.\r
+\r
+o Why the Lattice iCEstick, why not a more capable Xilinx **** eval board?\r
+ The iCEstick was chosen for two reasons. Cost and ease of programming. At $22\r
+ iCEstick is simply the lowest cost FPGA board BML could locate. Reason two\r
+ is that the iCEstick doesn't require a separate JTAG cable for configuration.\r
+ Most FPGA boards require JTAG access to the FPGA which necessitates as USB to\r
+ JTAG dongle, which themselves cost between $50 and $270. The Lattice iCEstick\r
+ brilliantly uses the FTDI FT2232H chip which contains 2 converters in one \r
+ chip. The "Converter A" port is dedicated for programming the SPI PROM. This\r
+ makes it possible for non-FPGA designers to buy a $22 iCEstick and load the\r
+ sump2 firmware without any additional purchase.\r
+\r
+o Why are advanced features like delayed trigger, nth trigger, etc not enabled?\r
+ Many advanced features in the sump2.v Verilog design file are not enabled as \r
+ they would not fit. The $5 Lattice iCEHX1K is a VERY small FPGA with only i\r
+ 1280 Logic Elements and 65Kb of RAM. The sump2 project barely fit and \r
+ requires 100% of the FPGA's 160 CLBs. For only $2 more, Lattice has a pin \r
+ compatible iCEHX4K with 3520 LEs and 82Kb of RAM, but unfortunately the \r
+ iCEstick eval board is only available with this smaller FPGA.\r
+\r
+o Is the iCEstick 5V tolerant?\r
+ No - definitely NOT. The FPGA's inputs are LVCMOS 3.3V only. If there is \r
+ enough interest, BML may design a simple 5V->3V shield that will plug into\r
+ the Pmod 12pin header. This board would probably be a 74LVC244A buffer and \r
+ some headers and most likely available from OSH-Park as a shared design.\r
+ Other shields could readily be designed for RS232,RS422,LVDS,CAN,etc.\r
+ If your 5V signal is fairly slow and you are willing to risk blowing the \r
+ input protection diodes of the $22 iCEstick, you could try a 330 to 1K series\r
+ resistor between your 5V device and the iCEstick. Only do this if desperate\r
+ however and are willing to replace your iCEstick from any potential damage.\r
+ Update: A OSH-Park PCB for a 5V tolerant shield is available now for $5.\r
+\r
+o Why 96 MSPS? Why not 100 MSPS?\r
+ The oscillator included on the iCEstick is 12 MHz and 96 MHz is what the PLL\r
+ is capable of synthesizing from that input frequency. Based on Nyquist, the\r
+ SUMP2 at 96 MSPS should be sufficient for sampling SPI signals up to 48 MHz.\r
+\r
+o What is Mesa Bus Protocol?\r
+ Mesa Bus Protocol is an open communications protocol for sending PCI'ish bus\r
+ cycles of 32bit Address and Data Reads and Writes over serial communication\r
+ channels like RS232,SPI,USB-VCP,SERDES,etc. The full Mesa Bus Protocol \r
+ provides for daisy chaining up to 250 devices on a single connection. The\r
+ limited resources of the iCEstick FPGA required that the daisy chain feature\r
+ not be supported. For SUMP2 on the iCEstick the MesaBus operates at 921,600\r
+ baud which is the maximum supported by standard Windows Com Port devices.\r
+\r
+o Will SUMP2 work with Sigrok software?\r
+ Maybe in the future - it would be up to the Sigrok developers. SUMP2 uses a\r
+ simple protocol for arming and dumping samples. It should be very feasible \r
+ for Sigrok software to be modified to work with SUMP2.\r
+\r
+o Does SUMP2 software do serial protocol analysis?\r
+ No. For actual decoding of serial streams ( UART, SPI, etc ) it is highly \r
+ recommended to invest in a Saleae. The Logic4 from Saleae may only be 4 bits\r
+ at 12 MSPS, but for $109 includes the entire Saleae protocol analysis \r
+ software and streams samples to system DRAM with almost unlimited depth.\r
+\r
+o What is bd_shell?\r
+ bd_shell ( or Backdoor Shell ) is a simple UNIX shell like interface to access\r
+ hardware. Combined with Mesa Bus Protocol, bd_shell provides a simple commmand\r
+ line interface for writing and reading hardware registers. It is inspired by \r
+ the poke and peek commands of BASIC time gone past. The bd_shell equivalent to\r
+ Poke is "w", and Peek is "r". The sump2.py application includes a bd_shell \r
+ interface as it is used as the inner workings for trigger settings, etc.\r
+\r
+o Why are two programs necessary? It would be better to just launch one program.\r
+ Please see the "sump2_execution.txt" document for steps on creating a simple\r
+ batch script to launch both python programs in correct order.\r
projects / BML_sump2 / blobdiff