DSO138_SourceCodes_v037.rar
authorJYE Tech <jyetek@gmail.com>
Sun, 28 Feb 2016 23:23:35 +0000 (00:23 +0100)
committerDobrica Pavlinusic <dpavlin@rot13.org>
Sun, 28 Feb 2016 23:23:35 +0000 (00:23 +0100)
109 files changed:
113-13801.c [new file with mode: 0644]
Board.c [new file with mode: 0644]
Board.h [new file with mode: 0644]
Command.c [new file with mode: 0644]
Command.h [new file with mode: 0644]
Common.c [new file with mode: 0644]
Common.h [new file with mode: 0644]
Eeprom.c [new file with mode: 0644]
Eeprom.h [new file with mode: 0644]
Libraries/CMSIS/CM3/CoreSupport/core_cm3.c [new file with mode: 0644]
Libraries/CMSIS/CM3/CoreSupport/core_cm3.h [new file with mode: 0644]
Libraries/CMSIS/CM3/CoreSupport/stm32f10x.h [new file with mode: 0644]
Libraries/CMSIS/CM3/CoreSupport/system_stm32f10x.c [new file with mode: 0644]
Libraries/CMSIS/CM3/CoreSupport/system_stm32f10x.h [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32F10x_CMSIS.html [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c [new file with mode: 0644]
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h [new file with mode: 0644]
Libraries/CMSIS/CMSIS debug support.htm [new file with mode: 0644]
Libraries/CMSIS/CMSIS_changes.htm [new file with mode: 0644]
Libraries/CMSIS/Documentation/CMSIS_Core.htm [new file with mode: 0644]
Libraries/CMSIS/License.doc [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/Release_Notes_for_STM32F10x_StdPeriph_Driver.html [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/misc.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c [new file with mode: 0644]
Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c [new file with mode: 0644]
Makefile [new file with mode: 0644]
STM32F10x_64k_20k_flash.ld [new file with mode: 0644]
Screen.c [new file with mode: 0644]
Screen.h [new file with mode: 0644]
libdso138.a [new file with mode: 0644]
libdso138.h [new file with mode: 0644]
readme.txt [new file with mode: 0644]
startup_stm32f10x_md.S [new file with mode: 0644]
stm32f10x_conf.h [new file with mode: 0644]
stm32f10x_it.c [new file with mode: 0644]
stm32f10x_it.h [new file with mode: 0644]
system_stm32f10x.c [new file with mode: 0644]

diff --git a/113-13801.c b/113-13801.c
new file mode 100644 (file)
index 0000000..d0eb83a
--- /dev/null
@@ -0,0 +1,150 @@
+//////////////////////////////////////////////////////////////////////////////\r
+//\r
+//     Filename:       113-13801.c\r
+//     Version:                \r
+//     Data:           \r
+//\r
+//     Author:         Liu, Zemin\r
+//     Company:        JYE Tech\r
+//\r
+//-----------------------------------------------------------------------------\r
+//\r
+//     Target:                 STM32F103C8 \r
+//     Tool chain:     CodeSourcery G++\r
+//\r
+//     Descriptions:   Main firmware for low-cost DSO kit\r
+//     PCB:            109-13800-00C\r
+//-----------------------------------------------------------------------------\r
+//     Required files:\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     ATTENTION: \r
+//-----------------------------------------------------------------------------\r
+//     Revision History:\r
+//\r
+//\r
+///////////////////////////////////////////////////////////////////////////////\r
+\r
+#include "stm32f10x.h"\r
+#include "stm32f10x_conf.h"\r
+\r
+#include "Common.h"\r
+#include "Board.h"\r
+#include       "Screen.h"\r
+#include       "Command.h"\r
+#include       "Eeprom.h"\r
+\r
+#include       "libdso138.h"\r
+\r
+\r
+int main (void)\r
+{\r
+ U16 tmp1, tmp2;\r
\r
+ Clock_Init();\r
\r
+ Port_Init();\r
+\r
+ // Check SW4 pin. If the pin is read LOW enter TEST mode\r
+ tmp1 = (PB_Port & PB_Bits) | ~PB_Bits;\r
+ if(!BitTest(tmp1, 0x8000)) {\r
+       // Enter TEST mode\r
+       TestMode();\r
+       }\r
\r
+ /* Unlock the Flash Program Erase controller */\r
+ FLASH_Unlock();\r
+\r
+ /* EEPROM Init */\r
+ EE_Init();\r
+\r
+ TFT_Init_Ili9341();\r
\r
+ USART1_Init();\r
+ uputs((U8 *)"Uart1 Ok\n\r", USART1);\r
+\r
+ SysTick_Init();\r
+ TIM3_Init();\r
+ TIM4_Init();\r
+\r
+ ADC2_Init();\r
\r
+ AppInit();  \r
\r
+ tmp1 = clBlack;\r
+ PutsGenic(24, 120, (U8 *)"FW: 113-13801-037", clWhite, tmp1, &ASC8X16);\r
+ PutsGenic(24, 140, (U8 *)LibVersion, clWhite, tmp1, &ASC8X16);\r
+ PutsGenic(24, 180, (U8 *)"Booting...", clWhite, tmp1, &ASC8X16);\r
+\r
+ // LED blink twice\r
+ LedBlink();\r
+\r
+ NVIC_Configuration();\r
+\r
+ Flags = 0;\r
\r
+// Uncomment the following line to disable display of scope panel\r
+// NoScopePanel = 1;\r
\r
+ while(1) {\r
+// ============================\r
+// Note:       Keep this section in the main loop for proper capture engine running\r
+//             even scope panel display is disabled.\r
+\r
+       DsoDisplay();\r
+\r
+       tmp1 = GetDsoStatus();\r
+\r
+// --------------------------------------------------------    \r
+       if(BitTest(tmp1, DSO_NormalDisplay)) {\r
+\r
+               // Add your diaplay codes here\r
+\r
+               \r
+               }\r
+// --------------------------------------------------------\r
+\r
+       if(GTimeout) {\r
+               GTimeout = 0;\r
+               StartCapture();\r
+               }\r
+       \r
+// ============================        \r
+\r
+\r
+       if(BitTest(Keypad.Flags, (1 << KF_DoKeyScan))) {\r
+               BitClr(Keypad.Flags, (1 << KF_DoKeyScan));\r
+               // Do key scan\r
+               KeyScan();\r
+               }\r
+\r
+       if(Keypad.KeyCode) {\r
+               // Process key code\r
+               KeyProc();\r
+               Keypad.KeyCode = 0;\r
+               }\r
+\r
+       if(GTimer == 0) {\r
+               if(BitTest(tmp1, DSO_CaptureDone)) {\r
+                       UpdateDisp(Disp_Trace);\r
+                       tmp2 = GetTimebase();\r
+                       if(tmp2 <= TB_1ms) {\r
+                               // Start next capture           \r
+                               StartCapture();\r
+                               }\r
+                       else {\r
+                               // Lower capture rate\r
+                               GTimer = 40;\r
+                               }\r
+                       }\r
+               }\r
+\r
+       \r
+       if(BitTest(tmp1, DSO_Rolling)) {\r
+               Rolling();\r
+               }\r
+\r
+       }\r
\r
+}\r
+\r
diff --git a/Board.c b/Board.c
new file mode 100644 (file)
index 0000000..db2823c
--- /dev/null
+++ b/Board.c
@@ -0,0 +1,1226 @@
+//////////////////////////////////////////////////////////////////////////////\r
+//\r
+//     Filename:       Board.c\r
+//     Version:                \r
+//     Data:           \r
+//\r
+//     Author:         Liu, Zemin
+//     Company:        JYE Tech Ltd.\r
+//     Web:            www.jyetech.com\r
+//
+//-----------------------------------------------------------------------------
+//
+//     Target:                 STM32F103C8\r
+//     Tool chain:     CodeSourcery G++\r
+//
+//-----------------------------------------------------------------------------\r
+//     Required files:\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Notes:\r
+//\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Revision History:\r
+//\r
+///////////////////////////////////////////////////////////////////////////////\r
+//
+//-----------------------------------------------------------------------------
+//     Includes
+//-----------------------------------------------------------------------------
+\r
+#include "stm32f10x.h"\r
+\r
+#include "Common.h"\r
+#include "Board.h"\r
+#include       "libdso138.h"\r
+\r
+// ===========================================================\r
+//     File Scope Variables\r
+// ===========================================================\r
+//\r
+       \r
+U16            GTimer;\r
+U8             GTimeout;\r
+\r
+U16            TimerKeyScan;\r
+\r
+//U8   GeneralBuf[50];\r
+\r
+// ===========================================================\r
+//     Function Definitions\r
+// ===========================================================\r
+\r
+//-----------------------------------------------------------------------------
+// Clock_Init\r
+//-----------------------------------------------------------------------------
+//\r
+void   Clock_Init(void)\r
+{\r
+ RCC->CR =  (1 << HSION)               /*!< Internal High Speed clock enable */\r
+                       |(0 << HSIRDY)          /*!< Internal High Speed clock ready flag */\r
+                       |(0x10 << HSITRIM)     /*!< Internal High Speed clock trimming */\r
+                       |(0 << HSICAL)          /*!< Internal High Speed clock Calibration */\r
+                       |(1 << HSEON)                   /*!< External High Speed clock enable */\r
+                       |(0 << HSERDY)          /*!< External High Speed clock ready flag */\r
+                       |(0 << HSEBYP)          /*!< External High Speed clock Bypass */\r
+                       |(0 << CSSON)           /*!< Clock Security System enable */\r
+                       |(0 << PLLON)                   /*!< PLL enable */\r
+                       |(0 << PLLRDY);         /*!< PLL clock ready flag */\r
+\r
+//     MCO[2:0] : Microcontroller clock output\r
+//             0xx: No clock\r
+//             100: System clock (SYSCLK) selected\r
+//             101: HSI clock selected\r
+//             110: HSE clock selected\r
+//             111: PLL clock divided by 2 selected\r
+//             \r
+//     USBPRE: USB prescaler\r
+//     Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before\r
+//     enabling the USB clock in the RCC_APB1ENR register. This bit can¡¯t be reset if the USB\r
+//     clock is enabled.\r
+//             0: PLL clock is divided by 1.5\r
+//             1: PLL clock is not divided\r
+//             \r
+//     PLLMUL[3:0] : PLL multiplication factor\r
+//     These bits are written by software to define the PLL multiplication factor. These bits can be\r
+//     written only when PLL is disabled.\r
+//             0000: PLL input clock x 2\r
+//             0001: PLL input clock x 3\r
+//             0010: PLL input clock x 4\r
+//             0011: PLL input clock x 5\r
+//             0100: PLL input clock x 6\r
+//             0101: PLL input clock x 7\r
+//             0110: PLL input clock x 8\r
+//             0111: PLL input clock x 9\r
+//             1000: PLL input clock x 10\r
+//             1001: PLL input clock x 11\r
+//             1010: PLL input clock x 12\r
+//             1011: PLL input clock x 13\r
+//             1100: PLL input clock x 14\r
+//             1101: PLL input clock x 15\r
+//             1110: PLL input clock x 16\r
+//             1111: PLL input clock x 16\r
+//\r
+//     PLLXTPRE: HSE divider for PLL entry\r
+//     Set and cleared by software to divide HSE before PLL entry. This bit can be written only\r
+//     when PLL is disabled.\r
+//             0: HSE clock not divided\r
+//             1: HSE clock divided by 2\r
+//             \r
+//     PLLSRC: PLL entry clock source\r
+//     Set and cleared by software to select PLL clock source. This bit can be written only when\r
+//     PLL is disabled.\r
+//             0: HSI oscillator clock / 2 selected as PLL input clock\r
+//             1: HSE oscillator clock selected as PLL input clock     \r
+//             \r
+//     ADCPRE[1:0] : ADC prescaler\r
+//     Set and cleared by software to select the frequency of the clock to the ADCs.\r
+//             00: PLCK2 divided by 2\r
+//             01: PLCK2 divided by 4\r
+//             10: PLCK2 divided by 6\r
+//             11: PLCK2 divided by 8\r
+//     \r
+//     PPRE2[2:0] : APB high-speed prescaler (APB2)\r
+//     Set and cleared by software to control the division factor of the APB high-speed clock\r
+//     (PCLK2).\r
+//             0xx: HCLK not divided\r
+//             100: HCLK divided by 2\r
+//             101: HCLK divided by 4\r
+//             110: HCLK divided by 8\r
+//             111: HCLK divided by 16\r
+\r
+//     PPRE1[2:0] : APB low-speed prescaler (APB1)\r
+//     Set and cleared by software to control the division factor of the APB low-speed clock\r
+//     (PCLK1).\r
+//     Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.\r
+//             0xx: HCLK not divided\r
+//             100: HCLK divided by 2\r
+//             101: HCLK divided by 4\r
+//             110: HCLK divided by 8\r
+//             111: HCLK divided by 16\r
+\r
+//     HPRE[3:0] : AHB prescaler\r
+//     Set and cleared by software to control the division factor of the AHB clock.\r
+//             0xxx: SYSCLK not divided\r
+//             1000: SYSCLK divided by 2\r
+//             1001: SYSCLK divided by 4\r
+//             1010: SYSCLK divided by 8\r
+//             1011: SYSCLK divided by 16\r
+//             1100: SYSCLK divided by 64\r
+//             1101: SYSCLK divided by 128\r
+//             1110: SYSCLK divided by 256\r
+//             1111: SYSCLK divided by 512     \r
+//             \r
+//     SWS[1:0] : System clock switch status\r
+//     Set and cleared by hardware to indicate which clock source is used as system clock.\r
+//             00: HSI oscillator used as system clock\r
+//             01: HSE oscillator used as system clock\r
+//             10: PLL used as system clock\r
+//             11: not applicable\r
+\r
+//     SW[1:0] : System clock switch\r
+//     Set and cleared by software to select SYSCLK source.\r
+//     Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of\r
+//     failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security\r
+//     System is enabled).\r
+//             00: HSI selected as system clock\r
+//             01: HSE selected as system clock\r
+//             10: PLL selected as system clock\r
+//             11: not allowed\r
+//\r
+ RCC->CFGR = (0 << SW)                 /*!< SW[1:0] bits (System clock Switch) */\r
+                       |(0 << SWS)                     /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+                       |(0 << HPRE)                    /*!< HPRE[3:0] bits (AHB prescaler)  [HCLK] */ \r
+                       |(0b100 << PPRE1)       /*!< PRE1[2:0] bits (APB1 prescaler) [PCLK1] */\r
+                       |(0 << PPRE2)                   /*!< PRE2[2:0] bits (APB2 prescaler) [PCLK2] */\r
+                       |(2 << ADCPRE)          /*!< ADCPRE[1:0] bits (ADC prescaler) */\r
+                       |(1 << PLLSRC)          /*!< PLL entry clock source */\r
+                       |(0 << PLLXTPRE)        /*!< HSE divider for PLL entry */\r
+                       |(7 << PLLMULL)         /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+                       |(0 << USBPRE)          /*!< USB Device prescaler */\r
+                       |(0 << MCO);                    /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+\r
+ RCC->CR =  (1 << HSION)               /*!< Internal High Speed clock enable */\r
+                       |(0 << HSIRDY)          /*!< Internal High Speed clock ready flag */\r
+                       |(0x10 << HSITRIM)     /*!< Internal High Speed clock trimming */\r
+                       |(0 << HSICAL)          /*!< Internal High Speed clock Calibration */\r
+                       |(1 << HSEON)                   /*!< External High Speed clock enable */\r
+                       |(0 << HSERDY)          /*!< External High Speed clock ready flag */\r
+                       |(0 << HSEBYP)          /*!< External High Speed clock Bypass */\r
+                       |(0 << CSSON)           /*!< Clock Security System enable */\r
+                       |(1 << PLLON)                   /*!< PLL enable */\r
+                       |(0 << PLLRDY);         /*!< PLL clock ready flag */\r
+\r
+\r
+ RCC->CIR = (0 << LSIRDYF)             /*!< LSI Ready Interrupt flag */\r
+                       |(0 << LSERDYF)         /*!< LSE Ready Interrupt flag */\r
+                       |(0 << HSIRDYF)         /*!< HSI Ready Interrupt flag */\r
+                       |(0 << HSERDYF)         /*!< HSE Ready Interrupt flag */\r
+                       |(0 << PLLRDYF)         /*!< PLL Ready Interrupt flag */\r
+                       |(0 << CSSF)                    /*!< Clock Security System Interrupt flag */\r
+                       |(0 << LSIRDYIE )       /*!< LSI Ready Interrupt Enable */\r
+                       |(0 << LSERDYIE)        /*!< LSE Ready Interrupt Enable */\r
+                       |(0 << HSIRDYIE)        /*!< HSI Ready Interrupt Enable */\r
+                       |(0 << HSERDYIE)        /*!< HSE Ready Interrupt Enable */\r
+                       |(0 << PLLRDYIE)        /*!< PLL Ready Interrupt Enable */\r
+                       |(0 << LSIRDYC)         /*!< LSI Ready Interrupt Clear */\r
+                       |(0 << LSERDYC)         /*!< LSE Ready Interrupt Clear */\r
+                       |(0 << HSIRDYC)         /*!< HSI Ready Interrupt Clear */\r
+                       |(0 << HSERDYC)         /*!< HSE Ready Interrupt Clear */\r
+                       |(0 << PLLRDYC)         /*!< PLL Ready Interrupt Clear */\r
+                       |(0 << CSSC);           /*!< Clock Security System Interrupt Clear */\r
+\r
+\r
+ RCC->APB2RSTR = (0 << AFIORST)        /*!< Alternate Function I/O reset */\r
+                       |(0 << IOPARST)         /*!< I/O port A reset */\r
+                       |(0 << IOPBRST)         /*!< I/O port B reset */\r
+                       |(0 << IOPCRST)         /*!< I/O port C reset */\r
+                       |(0 << IOPDRST)         /*!< I/O port D reset */\r
+                       |(0 << IOPERST)         /*!< I/O port E reset */\r
+                       |(0 << IOPFRST)         /*!< I/O port F reset */\r
+                       |(0 << IOPGRST)         /*!< I/O port G reset */\r
+                       |(0 << ADC1RST)         /*!< ADC 1 interface reset */\r
+                       |(0 << ADC2RST)         /*!< ADC 2 interface reset */\r
+                       |(0 << TIM1RST)         /*!< TIM1 Timer reset */\r
+                       |(0 << SPI1RST)         /*!< SPI 1 reset */\r
+                       |(0 << TIM8RST)         /*!< TIM8 Timer reset */\r
+                       |(0 << USART1RST)       /*!< USART1 reset */\r
+                       |(0 << ADC3RST);        /*!< ADC3 interface reset */\r
+\r
+ RCC->APB1RSTR = (0 << TIM2RST) /*!< Timer 2 reset */\r
+                       |(0 << TIM3RST)         /*!< Timer 3 reset */\r
+                       |(0 << TIM4RST)         /*!< Timer 4 reset */\r
+                       |(0 << TIM5RST)         /*!< Timer 5 reset */\r
+                       |(0 << TIM6RST)         /*!< Timer 6 reset */\r
+                       |(0 << TIM7RST)         /*!< Timer 7 reset */\r
+                       |(0 << WWDGRST)         /*!< Window Watchdog reset */\r
+                       |(0 << SPI2RST)         /*!< SPI 2 reset */\r
+                       |(0 << SPI3RST)         /*!< SPI 3 reset */\r
+                       |(0 << USART2RST)       /*!< USART 2 reset */\r
+                       |(0 << USART3RST)       /*!< RUSART 3 reset */\r
+                       |(0 << UART4RST )       /*!< UART 4 reset */\r
+                       |(0 << UART5RST)        /*!< UART 5 reset */\r
+                       |(0 << I2C1RST)         /*!< I2C 1 reset */\r
+                       |(0 << I2C2RST)         /*!< I2C 2 reset */\r
+                       |(0 << USBRST)          /*!< USB Device reset */\r
+                       |(0 << CAN1RST)         /*!< CAN1 reset */\r
+                       |(0 << BKPRST)          /*!< Backup interface reset */\r
+                       |(0 << PWRRST)          /*!< Power interface reset */\r
+                       |(0 << DACRST);         /*!< DAC interface reset */\r
+\r
\r
+ RCC->AHBENR = (0 << SDIOEN)\r
+                               |(0 << FSMCEN)\r
+                               |(0 << CRCEN)\r
+                               |(1 << FLITFEN)\r
+                               |(1 << SRAMEN)\r
+                               |(0 << DMA2EN)\r
+                               |(1 << DMA1EN);\r
+\r
+ RCC->APB1ENR = (0 << DACEN)\r
+                               |(0 << PWREN)\r
+                               |(0 << BKPEN)\r
+                               |(0 << CANEN)\r
+                               |(0 << USBEN)\r
+                               |(0 << I2C2EN)\r
+                               |(0 << I2C1EN)\r
+                               |(0 << UART5EN)\r
+                               |(0 << UART4EN)\r
+                               |(0 << USART3EN)\r
+                               |(0 << USART2EN)\r
+                               |(0 << SPI3EN)\r
+                               |(0 << SPI2EN)\r
+                               |(0 << WWDGEN)\r
+                               |(0 << TIM7EN)\r
+                               |(0 << TIM6EN)\r
+                               |(0 << TIM5EN)\r
+                               |(1 << TIM4EN)\r
+                               |(1 << TIM3EN)\r
+                               |(1 << TIM2EN);\r
+\r
+ RCC->APB2ENR = (0 << ADC3EN)\r
+                               |(1 << USART1EN)\r
+                               |(0 << TIM8EN)\r
+                               |(0 << SPI1EN)\r
+                               |(1 << TIM1EN)\r
+                               |(1 << ADC2EN)\r
+                               |(1 << ADC1EN)\r
+                               |(0 << IOPGEN)\r
+                               |(0 << IOPFEN)\r
+                               |(0 << IOPEEN)\r
+                               |(1 << IOPDEN)\r
+                               |(1 << IOPCEN)\r
+                               |(1 << IOPBEN)\r
+                               |(1 << IOPAEN)\r
+                               |(1 << AFIOEN);\r
+\r
+ RCC->BDCR = 0x00000000;\r
+ RCC->CSR = 0x00000000;\r
+\r
+ // Switch to HSE if it is ready\r
+ if(BitTest(RCC->CR, (1 << HSERDY))) {\r
+       RCC->CFGR &= ~RCC_CFGR_SW;\r
+       RCC->CFGR |= RCC_CFGR_SW_HSE;\r
+       }\r
+\r
+  // Switch to PLL if it is ready\r
+ if(BitTest(RCC->CR, (1 << PLLRDY))) {\r
+       RCC->CFGR &= ~RCC_CFGR_SW;\r
+       RCC->CFGR |= RCC_CFGR_SW_PLL;\r
+       }\r
+\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Misc_Init\r
+//-----------------------------------------------------------------------------
+\r
+//-----------------------------------------------------------------------------
+// PORT_Init
+//-----------------------------------------------------------------------------
+//
+// This routine configures the crossbar and GPIO ports.
+//
+void Port_Init(void)\r
+{\r
+ GPIOA->CRL = ((GPIO_CNF_AnalogIn | GPIO_Mode_In) << (0*4))    // ADC1_IN0\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (1*4))\r
+                       |((GPIO_CNF_Floating|GPIO_Mode_In) << (2*4))    \r
+                       |((GPIO_CNF_Floating |GPIO_Mode_In) << (3*4))           \r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (4*4))\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (5*4))\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (6*4))          \r
+                       |((GPIO_CNF_AF_PP | GPIO_Mode_Out50M) << (7*4));                //Test signal\r
+\r
+\r
+ GPIOA->CRH = ((GPIO_CNF_Floating| GPIO_Mode_In) << (8 - 8)*4)         // TrigIn\r
+                       |((GPIO_CNF_AF_PP |GPIO_Mode_Out50M) << (9 - 8)*4)      // TX1\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (10 - 8)*4)             // RX1\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (11 - 8)*4)\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (12 - 8)*4)\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (13 - 8)*4)\r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (14 - 8)*4)\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (15 - 8)*4);   // LED\r
+\r
+ GPIOA->ODR = 0xFFFF;\r
+\r
+ GPIOB->CRL = ((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (0*4))           // TFT port - D0\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (1*4))         // TFT port - D1\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (2*4))         // TFT port - D2\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (3*4))         // TFT port - D3\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (4*4))         // TFT port - D4\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (5*4))         // TFT port - D5\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (6*4))         // TFT port - D6        \r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (7*4));                // TFT port - D7                \r
+\r
+ GPIOB->CRH = ((GPIO_CNF_AF_PP| GPIO_Mode_Out50M) << ((8 - 8)*4))              // Output, Trigger level\r
+                       |((GPIO_CNF_AF_PP| GPIO_Mode_Out50M) << ((9 - 8)*4))            // Output, Gen\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << ((10 - 8)*4))          // Output, TFT_nRD\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << ((11 - 8)*4))          // Output, TFT_nReset\r
+                       |((GPIO_CNF_IPU | GPIO_Mode_In) << ((12 - 8)*4))                // SW4  \r
+                       |((GPIO_CNF_IPU | GPIO_Mode_In) << ((13 - 8)*4))                // SW3\r
+                       |((GPIO_CNF_IPU | GPIO_Mode_In) << ((14 - 8)*4))                // SW2\r
+                       |((GPIO_CNF_IPU | GPIO_Mode_In) << ((15 - 8)*4));               // SW1\r
+\r
+ GPIOB->ODR = 0xFFFF;\r
+\r
+ GPIOC->CRH = ((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (13 - 8)*4)              // TFT_nCS\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (14 - 8)*4)            // TFT_RS\r
+                       |((GPIO_CNF_GP_PP | GPIO_Mode_Out50M) << (15 - 8)*4);           // TFT_nWR\r
+\r
+ GPIOC->ODR = 0xFFFF;\r
\r
+ GPIOD->CRL = ((GPIO_CNF_Floating | GPIO_Mode_In) << (0*4))            \r
+                       |((GPIO_CNF_Floating | GPIO_Mode_In) << (1*4));         \r
+\r
+ // Remap to make PB3 & PB4 available\r
+ AFIO->MAPR &= ~AFIO_MAPR_SWJ_CFG;\r
+ AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;\r
\r
+}\r
+\r
+void   USART1_Init(void)\r
+{\r
+ USART_InitTypeDef USART_InitStructure;\r
\r
+  USART_InitStructure.USART_BaudRate = 38400;\r
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;\r
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;\r
+  USART_InitStructure.USART_Parity = USART_Parity_No;\r
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;\r
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+  \r
+  /* Configure USART1 */\r
+  USART_Init(USART1, &USART_InitStructure);\r
+  \r
+  /* Enable the USART1 */\r
+  USART_Cmd(USART1, ENABLE);\r
+\r
+}\r
+\r
+void   UartPutc(U8 ch, USART_TypeDef* USARTx)\r
+{\r
+ while(USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET) {\r
+       }\r
+ USART_SendData(USARTx, ch);\r
+}\r
+\r
+void   uputs(U8 *s, USART_TypeDef* USARTx)\r
+{\r
+ while(*s != 0) {\r
+       UartPutc(*s, USARTx);\r
+       s++;\r
+       }\r
+}\r
+\r
+ void  TIM3_Init(void)\r
+{\r
+ // Disable counter first\r
+ TIM3->CR1 = (0 << CEN)                //!<Counter enable //\r
+               | (0 << UDIS)                           //!<Update disable //\r
+               | (0 << URS)                    //!<Update request source //\r
+               | (0 << OPM)                    //!<One pulse mode //\r
+               | (0 << DIR)                    //!<Direction. 0: Up, 1: Down\r
+               | (0 << CMS)                    //!<CMS[1:0] bits (Center-aligned mode selection) //\r
+               | (1 << ARPE)                   //!<Auto-reload preload enable //\r
+               | (0 << CKD);                   //!<CKD[1:0] bits (clock division for filtering) 0 = 1/1, 1 = 1/2, 2 = 1/4\r
+\r
+ TIM3->CR2 = (0 << CCPC)               //<Capture/Compare Preloaded Control //\r
+               | (0 << CCUS)                           //<Capture/Compare Control Update Selection //\r
+               | (0 << CCDS)                           //<Capture/Compare DMA Selection //\r
+               | (0 << MMS)                    //<MMS[2:0] bits (Master Mode Selection) //\r
+               | (0 << TI1S)                           //<TI1 Selection //\r
+               | (0 << OIS1)                           //<Output Idle state 1 (OC1 output) //\r
+               | (0 << OIS1N)                          //<Output Idle state 1 (OC1N output) //\r
+               | (0 << OIS2)                           //<Output Idle state 2 (OC2 output) //\r
+               | (0 << OIS2N)                          //<Output Idle state 2 (OC2N output) //\r
+               | (0 << OIS3)                           //<Output Idle state 3 (OC3 output) //\r
+               | (0 << OIS3N)                          //<Output Idle state 3 (OC3N output) //\r
+               | (0 << OIS4);                          //<Output Idle state 4 (OC4 output) //\r
+\r
+ TIM3->SMCR = (0 << SMS)               //<SMS[2:0] bits (Slave mode selection) //\r
+               | (0 << TS)                     //<TS[2:0] bits (Trigger selection) //\r
+               | (0 << MSM)                    //<Master/slave mode //\r
+               | (0 << ETF)                    //<ETF[3:0] bits (External trigger filter) //\r
+               | (0 << ETPS)                           //<ETPS[1:0] bits (External trigger prescaler) //\r
+               | (0 << ECE)                    //<External clock enable //\r
+               | (0 << ETP);                           //<External trigger polarity //\r
+\r
\r
+ TIM3->DIER = (0 << UIE)               //<Update interrupt enable //\r
+               | (0 << CC1IE)                          //<Capture/Compare 1 interrupt enable //\r
+               | (0 << CC2IE)                          //<Capture/Compare 2 interrupt enable //\r
+               | (0 << CC3IE)                          //<Capture/Compare 3 interrupt enable //\r
+               | (0 << CC4IE)                          //<Capture/Compare 4 interrupt enable //\r
+               | (0 << COMIE)                          //<COM interrupt enable //\r
+               | (0 << TIE)                    //<Trigger interrupt enable //\r
+               | (0 << BIE)                    //<Break interrupt enable //\r
+               | (0 << UDE)                    //<Update DMA request enable //\r
+               | (0 << CC1DE)                          //<Capture/Compare 1 DMA request enable //\r
+               | (0 << CC2DE)                          //<Capture/Compare 2 DMA request enable //\r
+               | (0 << CC3DE)                          //<Capture/Compare 3 DMA request enable //\r
+               | (0 << CC4DE)                          //<Capture/Compare 4 DMA request enable //\r
+               | (0 << COMDE)                  //<COM DMA request enable //\r
+               | (0 << TDE);                           //<Trigger DMA request enable //\r
+\r
\r
+ TIM3->SR = 0x0000;\r
+ TIM3->EGR = 0x0000;\r
\r
+//----------------------------------------------------------------------------\r
+// TIMx capture/compare usage (x = 2 ~ 5, n = 1 ~ 4)\r
+//\r
+//     CCnS[1:0] :\r
+//             00: CCn channel is configured as output.\r
+//             01: CCn channel is configured as input, ICn is mapped on TI1.\r
+//             10: CCn channel is configured as input, ICn is mapped on TI2.\r
+//             11: CCn channel is configured as input, ICn is mapped on TRC. This mode is working only\r
+//                     if an internal trigger input is selected through TS bit (TIMx_SMCR register)\r
+//             Note:   CCnS bits are writable only when the channel is OFF (CCnE = 0 in TIMx_CCER).\r
+//                             Output compare mode\r
+//\r
+//     OCnM[2:0] :\r
+//             000: Frozen\r
+//             001: Set channel n to active level on match. \r
+//             010: Set channel n to inactive level on match. \r
+//             011: Toggle - OCnREF toggles when TIMx_CNT=TIMx_CCRn.\r
+//             100: Force inactive level - OCnREF is forced low.\r
+//             101: Force active level - OCnREF is forced high.\r
+//             110: PWM mode 1 - In upcounting, channel n is active as long as TIMx_CNT<TIMx_CCRn\r
+//                     else inactive. In downcounting, channel 1 is inactive (OCnREF=0) as long as\r
+//                     TIMx_CNT>TIMx_CCRn else active (OCnREF=1).\r
+//             111: PWM mode 2 - In upcounting, channel n is inactive as long as\r
+//                     TIMx_CNT<TIMx_CCRn else active. In downcounting, channel n is active as long as\r
+//                     TIMx_CNT>TIMx_CCRn else inactive.\r
+//             Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed\r
+//                             (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).\r
+//                       2: In PWM mode 1 or 2, the OCREF level changes only when the result of the\r
+//                             comparison changes or when the output compare mode switches from "frozen" mode\r
+//                             to "PWM" mode.\r
+//             \r
+//     ICnPSC[1:0] :\r
+//                     This bit-field defines the ratio of the prescaler acting on CCn input (ICn).\r
+//                     The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register).\r
+//             00: no prescaler, capture is done each time an edge is detected on the capture input.\r
+//             01: capture is done once every 2 events.\r
+//             10: capture is done once every 4 events.\r
+//             11: capture is done once every 8 events.\r
+//             \r
+//     ICnF[3:0] :\r
+//                     This bit-field defines the frequency used to sample TIn input and the length of the digital\r
+//                     filter applied to TIn. The digital filter is made of an event counter in which N events are\r
+//                     needed to validate a transition on the output:\r
+//             0000: No filter, sampling is done at fDTS.\r
+//             0001: fSAMPLING=fCK_INT, N=2.\r
+//             0010: fSAMPLING=fCK_INT, N=4.\r
+//             0011: fSAMPLING=fCK_INT, N=8.\r
+//             0100: fSAMPLING=fDTS/2, N=6.\r
+//             0101: fSAMPLING=fDTS/2, N=8.\r
+//             0110: fSAMPLING=fDTS/4, N=6.\r
+//             0111: fSAMPLING=fDTS/4, N=8.\r
+//             1000: fSAMPLING=fDTS/8, N=6.\r
+//             1001: fSAMPLING=fDTS/8, N=8.\r
+//             1010: fSAMPLING=fDTS/16, N=5.\r
+//             1011: fSAMPLING=fDTS/16, N=6.\r
+//             1100: fSAMPLING=fDTS/16, N=8.\r
+//             1101: fSAMPLING=fDTS/32, N=5.\r
+//             1110: fSAMPLING=fDTS/32, N=6.\r
+//             1111: fSAMPLING=fDTS/32, N=8.\r
+//                             Note:   In current silicon revision, fDTS is replaced in the formula by CK_INT \r
+//                                             when ICnF[3:0]= 1, 2 or 3.\r
+//             \r
+// Output compare mode\r
+ TIM3->CCMR1 = (0 << CC1S)             //!<CC1S[1:0] bits (Capture/Compare 1 Selection) \r
+               | (0 << OC1FE)                          //!<Output Compare 1 Fast enable \r
+               | (0 << OC1PE)                          //!<Output Compare 1 Preload enable \r
+               | (0 << OC1M)                   //!<OC1M[2:0] bits (Output Compare 1 Mode) \r
+               | (0 << OC1CE)                          //!<Output Compare 1Clear Enable \r
+               | (0 << CC2S)                           //!<CC2S[1:0] bits (Capture/Compare 2 Selection) \r
+               | (0 << OC2FE)                          //!<Output Compare 2 Fast enable \r
+               | (0 << OC2PE)                          //!<Output Compare 2 Preload enable \r
+               | (3 << OC2M)                           //!<OC2M[2:0] bits (Output Compare 2 Mode) \r
+               | (0 << OC2CE);                 //!<Output Compare 2 Clear Enable \r
+\r
+// Input capture mode\r
+// TIM3->CCMR1 = (0 << CC1S)           //!<CC1S[1:0] bits (Capture/Compare 1 Selection) \r
+//             | (0 << IC1PSC)                 //!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) \r
+//             | (0 << IC1F)                           //!<IC1F[3:0] bits (Input Capture 1 Filter) \r
+//             | (0 << CC2S)                           //!<CC2S[1:0] bits (Capture/Compare 2 Selection) \r
+//             | (0 << IC2PSC)                 //!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) \r
+//             | (0 << IC2F);                          //!<IC2F[3:0] bits (Input Capture 2 Filter) \r
+\r
+// Output compare mode\r
+ TIM3->CCMR2 = (0 << CC3S)             //!<CC3S[1:0] bits (Capture/Compare 3 Selection) \r
+               | (0 << OC3FE)                          //!<Output Compare 3 Fast enable \r
+               | (0 << OC3PE)                          //!<Output Compare 3 Preload enable \r
+               | (0 << OC3M)                           //!<OC3M[2:0] bits (Output Compare 3 Mode) \r
+               | (0 << OC3CE)                          //!<Output Compare 3Clear Enable \r
+               | (0 << CC4S)                           //!<CC4S[1:0] bits (Capture/Compare 4 Selection) \r
+               | (0 << OC4FE)                          //!<Output Compare 4 Fast enable \r
+               | (0 << OC4PE)                          //!<Output Compare 4 Preload enable \r
+               | (0 << OC4M)                           //!<OC4M[2:0] bits (Output Compare 4 Mode) \r
+               | (0 << OC4CE);                 //!<Output Compare 4 Clear Enable \r
+\r
+// Input capture mode\r
+// TIM3->CCMR2 = (0 << CC3S)           //!<CC3S[1:0] bits (Capture/Compare 3 Selection) \r
+//             | (0 << IC3PSC)                 //!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) \r
+//             | (0 << IC3F)                           //!<IC3F[3:0] bits (Input Capture 3 Filter) \r
+//             | (0 << CC4S)                           //!<CC4S[1:0] bits (Capture/Compare 4 Selection) \r
+//             | (0 << IC4PSC)                 //!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) \r
+//             | (0 << IC4F);                          //!<IC4F[3:0] bits (Input Capture 4 Filter) \r
+\r
+ TIM3->CCER = (0 << CC1E)              //<Capture/Compare 1 output enable //\r
+               | (0 << CC1P)                           //<Capture/Compare 1 output Polarity //\r
+               | (0 << CC1NE)                          //<Capture/Compare 1 Complementary output enable //\r
+               | (0 << CC1NP)                          //<Capture/Compare 1 Complementary output Polarity //\r
+               | (1 << CC2E)                           //<Capture/Compare 2 output enable //\r
+               | (0 << CC2P)                           //<Capture/Compare 2 output Polarity //\r
+               | (0 << CC2NE)                          //<Capture/Compare 2 Complementary output enable //\r
+               | (0 << CC2NP)                          //<Capture/Compare 2 Complementary output Polarity //\r
+               | (0 << CC3E)                           //<Capture/Compare 3 output enable //\r
+               | (0 << CC3P)                           //<Capture/Compare 3 output Polarity //\r
+               | (0 << CC3NE)                          //<Capture/Compare 3 Complementary output enable //\r
+               | (0 << CC3NP)                          //<Capture/Compare 3 Complementary output Polarity //\r
+               | (0 << CC4E)                           //<Capture/Compare 4 output enable //\r
+               | (0 << CC4P);                           //<Capture/Compare 4 output Polarity //\r
+\r
\r
+ TIM3->CNT = 0x0000;\r
\r
+ TIM3->PSC = 3600 - 1;                 // 0.5ms clock cycle\r
\r
+ TIM3->ARR = 10 - 1;\r
\r
+ TIM3->CCR1 = 5;\r
+ TIM3->CCR2 = 5;\r
+ TIM3->CCR3 = 0x0000;\r
+ TIM3->CCR4 = 0x0000;\r
+ TIM3->DCR = 0x0000;\r
+ TIM3->DMAR = 0x0000;\r
+\r
+ TIM3->CR1 = (1 << CEN)                //<Counter enable //\r
+               | (0 << UDIS)                           //<Update disable //\r
+               | (0 << URS)                    //<Update request source //\r
+               | (0 << OPM)                    //<One pulse mode //\r
+               | (0 << DIR)                    //<Direction //\r
+               | (0 << CMS)                    //<CMS[1:0] bits (Center-aligned mode selection) //\r
+               | (1 << ARPE)                   //<Auto-reload preload enable //\r
+               | (0 << CKD);                   //<CKD[1:0] bits (clock division) //\r
+\r
+}\r
+\r
+void   TIM4_Init(void)\r
+{\r
+ // Disable counter first\r
+ TIM4->CR1 = (0 << CEN)                //!<Counter enable //\r
+               | (0 << UDIS)                           //!<Update disable //\r
+               | (0 << URS)                    //!<Update request source //\r
+               | (0 << OPM)                    //!<One pulse mode //\r
+               | (0 << DIR)                    //!<Direction. 0: Up, 1: Down\r
+               | (0 << CMS)                    //!<CMS[1:0] bits (Center-aligned mode selection) //\r
+               | (1 << ARPE)                   //!<Auto-reload preload enable //\r
+               | (0 << CKD);                   //!<CKD[1:0] bits (clock division for filtering) 0 = 1/1, 1 = 1/2, 2 = 1/4\r
+\r
+ TIM4->CR2 = (0 << CCPC)               //!<Capture/Compare Preloaded Control //\r
+               | (0 << CCUS)                           //!<Capture/Compare Control Update Selection //\r
+               | (0 << CCDS)                           //!<Capture/Compare DMA Selection //\r
+               | (0 << MMS)                    //!<MMS[2:0] bits (Master Mode Selection) //\r
+               | (0 << TI1S)                           //!<TI1 Selection //\r
+               | (0 << OIS1)                           //!<Output Idle state 1 (OC1 output) //\r
+               | (0 << OIS1N)                          //!<Output Idle state 1 (OC1N output) //\r
+               | (0 << OIS2)                           //!<Output Idle state 2 (OC2 output) //\r
+               | (0 << OIS2N)                          //!<Output Idle state 2 (OC2N output) //\r
+               | (0 << OIS3)                           //!<Output Idle state 3 (OC3 output) //\r
+               | (0 << OIS3N)                          //!<Output Idle state 3 (OC3N output) //\r
+               | (0 << OIS4);                          //!<Output Idle state 4 (OC4 output) //\r
+\r
+ TIM4->SMCR = (0 << SMS)               //!<SMS[2:0] bits (Slave mode selection) //\r
+               | (0 << TS)                     //!<TS[2:0] bits (Trigger selection) //\r
+               | (0 << MSM)                    //!<Master/slave mode //\r
+               | (0 << ETF)                    //!<ETF[3:0] bits (External trigger filter) //\r
+               | (0 << ETPS)                           //!<ETPS[1:0] bits (External trigger prescaler) //\r
+               | (0 << ECE)                    //!<External clock enable //\r
+               | (0 << ETP);                           //!<External trigger polarity //\r
+\r
\r
+ TIM4->SR = 0x0000;\r
+ TIM4->EGR = 0x0000;\r
\r
+//----------------------------------------------------------------------------\r
+// TIMx capture/compare usage (x = 2 ~ 5, n = 1 ~ 4)\r
+//\r
+//     CCnS[1:0] :\r
+//             00: CCn channel is configured as output.\r
+//             01: CCn channel is configured as input, ICn is mapped on TI1.\r
+//             10: CCn channel is configured as input, ICn is mapped on TI2.\r
+//             11: CCn channel is configured as input, ICn is mapped on TRC. This mode is working only\r
+//                     if an internal trigger input is selected through TS bit (TIMx_SMCR register)\r
+//             Note:   CCnS bits are writable only when the channel is OFF (CCnE = 0 in TIMx_CCER).\r
+//                             Output compare mode\r
+//\r
+//     OCnM[2:0] :\r
+//             000: Frozen\r
+//             001: Set channel n to active level on match. \r
+//             010: Set channel n to inactive level on match. \r
+//             011: Toggle - OCnREF toggles when TIMx_CNT=TIMx_CCRn.\r
+//             100: Force inactive level - OCnREF is forced low.\r
+//             101: Force active level - OCnREF is forced high.\r
+//             110: PWM mode 1 - In upcounting, channel n is active as long as TIMx_CNT<TIMx_CCRn\r
+//                     else inactive. In downcounting, channel 1 is inactive (OCnREF=0) as long as\r
+//                     TIMx_CNT>TIMx_CCRn else active (OCnREF=1).\r
+//             111: PWM mode 2 - In upcounting, channel n is inactive as long as\r
+//                     TIMx_CNT<TIMx_CCRn else active. In downcounting, channel n is active as long as\r
+//                     TIMx_CNT>TIMx_CCRn else inactive.\r
+//             Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed\r
+//                             (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).\r
+//                       2: In PWM mode 1 or 2, the OCREF level changes only when the result of the\r
+//                             comparison changes or when the output compare mode switches from "frozen" mode\r
+//                             to "PWM" mode.\r
+//             \r
+//     ICnPSC[1:0] :\r
+//                     This bit-field defines the ratio of the prescaler acting on CCn input (ICn).\r
+//                     The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register).\r
+//             00: no prescaler, capture is done each time an edge is detected on the capture input.\r
+//             01: capture is done once every 2 events.\r
+//             10: capture is done once every 4 events.\r
+//             11: capture is done once every 8 events.\r
+//             \r
+//     ICnF[3:0] :\r
+//                     This bit-field defines the frequency used to sample TIn input and the length of the digital\r
+//                     filter applied to TIn. The digital filter is made of an event counter in which N events are\r
+//                     needed to validate a transition on the output:\r
+//             0000: No filter, sampling is done at fDTS.\r
+//             0001: fSAMPLING=fCK_INT, N=2.\r
+//             0010: fSAMPLING=fCK_INT, N=4.\r
+//             0011: fSAMPLING=fCK_INT, N=8.\r
+//             0100: fSAMPLING=fDTS/2, N=6.\r
+//             0101: fSAMPLING=fDTS/2, N=8.\r
+//             0110: fSAMPLING=fDTS/4, N=6.\r
+//             0111: fSAMPLING=fDTS/4, N=8.\r
+//             1000: fSAMPLING=fDTS/8, N=6.\r
+//             1001: fSAMPLING=fDTS/8, N=8.\r
+//             1010: fSAMPLING=fDTS/16, N=5.\r
+//             1011: fSAMPLING=fDTS/16, N=6.\r
+//             1100: fSAMPLING=fDTS/16, N=8.\r
+//             1101: fSAMPLING=fDTS/32, N=5.\r
+//             1110: fSAMPLING=fDTS/32, N=6.\r
+//             1111: fSAMPLING=fDTS/32, N=8.\r
+//                             Note:   In current silicon revision, fDTS is replaced in the formula by CK_INT \r
+//                                             when ICnF[3:0]= 1, 2 or 3.\r
+//             \r
+// Output compare mode\r
+// CH3 for VGEN generation\r
+// -- Set OC3 to output mode (CC3S[1:0] = 00)\r
+// -- Set output to PWM mode 1 (OC3M[2:0] = 110)\r
+// -- Set OC4 to output mode (CC4S[1:0] = 00)\r
+// -- Set output to PWM mode 1 (OC4M[2:0] = 110)\r
+\r
+ TIM4->CCMR1 = (0 << CC1S)             //!<CC1S[1:0] bits (Capture/Compare 1 Selection) \r
+               | (0 << OC1FE)                          //!<Output Compare 1 Fast enable \r
+               | (0 << OC1PE)                          //!<Output Compare 1 Preload enable \r
+               | (0 << OC1M)                   //!<OC1M[2:0] bits (Output Compare 1 Mode) \r
+               | (0 << OC1CE)                          //!<Output Compare 1Clear Enable \r
+               | (0 << CC2S)                           //!<CC2S[1:0] bits (Capture/Compare 2 Selection) \r
+               | (0 << OC2FE)                          //!<Output Compare 2 Fast enable \r
+               | (0 << OC2PE)                          //!<Output Compare 2 Preload enable \r
+               | (0 << OC2M)                           //!<OC2M[2:0] bits (Output Compare 2 Mode) \r
+               | (0 << OC2CE);                 //!<Output Compare 2 Clear Enable \r
+\r
+// Input capture mode\r
+/*\r
+ TIM4->CCMR1 = (0 << CC1S)             //!<CC1S[1:0] bits (Capture/Compare 1 Selection) \r
+               | (0 << IC1PSC)                 //!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) \r
+               | (0 << IC1F)                           //!<IC1F[3:0] bits (Input Capture 1 Filter) \r
+               | (0 << CC2S)                           //!<CC2S[1:0] bits (Capture/Compare 2 Selection) \r
+               | (0 << IC2PSC)                 //!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) \r
+               | (0 << IC2F);                          //!<IC2F[3:0] bits (Input Capture 2 Filter) \r
+*/\r
+\r
+// Output compare mode\r
+ TIM4->CCMR2 = (0 << CC3S)             //!<CC3S[1:0] bits (Capture/Compare 3 Selection) \r
+               | (0 << OC3FE)                          //!<Output Compare 3 Fast enable \r
+               | (0 << OC3PE)                          //!<Output Compare 3 Preload enable \r
+               | (0x06 << OC3M)                //!<OC3M[2:0] bits (Output Compare 3 Mode) \r
+               | (0 << OC3CE)                          //!<Output Compare 3Clear Enable \r
+               | (0 << CC4S)                           //!<CC4S[1:0] bits (Capture/Compare 4 Selection) \r
+               | (0 << OC4FE)                          //!<Output Compare 4 Fast enable \r
+               | (0 << OC4PE)                          //!<Output Compare 4 Preload enable \r
+               | (0x06 << OC4M)                        //!<OC4M[2:0] bits (Output Compare 4 Mode) \r
+               | (0 << OC4CE);                 //!<Output Compare 4 Clear Enable \r
+\r
+// Input capture mode\r
+/*\r
+ TIM4->CCMR2 = (0 << CC3S)             //!<CC3S[1:0] bits (Capture/Compare 3 Selection) \r
+               | (0 << IC3PSC)                 //!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) \r
+               | (0 << IC3F)                           //!<IC3F[3:0] bits (Input Capture 3 Filter) \r
+               | (0 << CC4S)                           //!<CC4S[1:0] bits (Capture/Compare 4 Selection) \r
+               | (0 << IC4PSC)                 //!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) \r
+               | (0 << IC4F);                          //!<IC4F[3:0] bits (Input Capture 4 Filter) \r
+*/\r
+\r
+ TIM4->CCER = (0 << CC1E)              //!<Capture/Compare 1 output enable //\r
+               | (0 << CC1P)                           //!<Capture/Compare 1 output Polarity //\r
+               | (0 << CC1NE)                          //!<Capture/Compare 1 Complementary output enable //\r
+               | (0 << CC1NP)                          //!<Capture/Compare 1 Complementary output Polarity //\r
+               | (0 << CC2E)                           //!<Capture/Compare 2 output enable //\r
+               | (0 << CC2P)                           //!<Capture/Compare 2 output Polarity //\r
+               | (0 << CC2NE)                          //!<Capture/Compare 2 Complementary output enable //\r
+               | (0 << CC2NP)                          //!<Capture/Compare 2 Complementary output Polarity //\r
+               | (1 << CC3E)                           //!<Capture/Compare 3 output enable //\r
+               | (0 << CC3P)                           //!<Capture/Compare 3 output Polarity //\r
+               | (0 << CC3NE)                          //!<Capture/Compare 3 Complementary output enable //\r
+               | (0 << CC3NP)                          //!<Capture/Compare 3 Complementary output Polarity //\r
+               | (1 << CC4E)                           //!<Capture/Compare 4 output enable //\r
+               | (0 << CC4P);                           //!<Capture/Compare 4 output Polarity //\r
+\r
\r
+ TIM4->CNT = 0x0000;\r
\r
+ TIM4->PSC = 1 - 1;            // Make 1M (36M/36) as basic clock\r
\r
+ TIM4->ARR = 4096 - 1; //  1KHz\r
\r
+ TIM4->CCR1 = 0x0000;  // This value must be set to smaller than ARR. Otherwise there is no\r
+                                               //      compare match and no output generated at pin.\r
+ TIM4->CCR2 = 0x0000;\r
+ TIM4->CCR3 = 0x800 - 1;\r
+ TIM4->CCR4 = 0x400 - 1;\r
+ TIM4->DCR = 0x0000;\r
+ TIM4->DMAR = 0x0000;\r
+\r
+ TIM4->DIER = (0 << UIE)               //!<Update interrupt enable //\r
+               | (0 << CC1IE)                          //!<Capture/Compare 1 interrupt enable //\r
+               | (0 << CC2IE)                          //!<Capture/Compare 2 interrupt enable //\r
+               | (0 << CC3IE)                          //!<Capture/Compare 3 interrupt enable //\r
+               | (0 << CC4IE)                          //!<Capture/Compare 4 interrupt enable //\r
+               | (0 << COMIE)                          //!<COM interrupt enable //\r
+               | (0 << TIE)                    //!<Trigger interrupt enable //\r
+               | (0 << BIE)                    //!<Break interrupt enable //\r
+               | (0 << UDE)                    //!<Update DMA request enable //\r
+               | (0 << CC1DE)                          //!<Capture/Compare 1 DMA request enable //\r
+               | (0 << CC2DE)                          //!<Capture/Compare 2 DMA request enable //\r
+               | (0 << CC3DE)                          //!<Capture/Compare 3 DMA request enable //\r
+               | (0 << CC4DE)                          //!<Capture/Compare 4 DMA request enable //\r
+               | (0 << COMDE)                  //!<COM DMA request enable //\r
+               | (0 << TDE);                           //!<Trigger DMA request enable //\r
+\r
+ TIM4->CR1 = (1 << CEN)                //!<Counter enable //\r
+               | (0 << UDIS)                           //!<Update disable //\r
+               | (0 << URS)                    //!<Update request source //\r
+               | (0 << OPM)                    //!<One pulse mode //\r
+               | (0 << DIR)                    //!<Direction //\r
+               | (0 << CMS)                    //!<CMS[1:0] bits (Center-aligned mode selection) //\r
+               | (1 << ARPE)                   //!<Auto-reload preload enable //\r
+               | (0 << CKD);                   //!<CKD[1:0] bits (clock division) //\r
+\r
+}\r
+\r
+\r
+void   SysTick_Init(void)\r
+{\r
+ SysTick->VAL = 0;                             // Write this register will clear itself and the settings in \r
+                                                               //      SysTick->CTRL\r
+                                                               \r
+ SysTick->CTRL = (1 << SysTick_ENABLE)         \r
+                               | (1 << SysTick_TICKINT)                // Counting down to 0 pends the SysTick handler \r
+                               | (1 << SysTick_CLKSOURCE)      // Clock source. 0 = HCLK/8; 1 = HCLK\r
+                               | (0 << SysTick_COUNTFLAG);     // Count Flag\r
+\r
+ SysTick->LOAD = 72000;\r
+\r
+// SysTick->CALRB         \r
+// This register is read-only. When clock source is set to HCLK/8 (CLKSOURCE bit is 0) the \r
+//     TENMS value in this register will be used to generate 1ms tick.\r
+//\r
+\r
+}\r
+\r
+\r
+void   ADC2_Init(void)\r
+{\r
+// NOTE: Remember to program ADC clock in RCC->CFGR\r
+\r
+  ADC2->SR = (0 << AWD)                         /*!<Analog watchdog flag */\r
+               | (0 << EOC)                              /*!<End of conversion */\r
+               | (0 << JEOC)                            /*!<Injected channel end of conversion */\r
+               | (0 << JSTRT)                             /*!<Injected channel Start flag */\r
+               | (0 << STRT);                             /*!<Regular channel Start flag */\r
+       \r
+  ADC2->CR1 = (0 << AWDCH)            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+                       | (0 << EOCIE)           /*!<Interrupt enable for EOC */\r
+                       | (0 << AWDIE)              /*!<AAnalog Watchdog interrupt enable */\r
+                       | (0 << JEOCIE)          /*!<Interrupt enable for injected channels */\r
+                       | (0 << SCAN )           /*!<Scan mode */\r
+                       | (0 << AWDSGL)             /*!<Enable the watchdog on a single channel in scan mode */\r
+                       | (0 << JAUTO)            /*!<Automatic injected group conversion */\r
+                       | (0 << DISCEN)            /*!<Discontinuous mode on regular channels */\r
+                       | (0 << JDISCEN)             /*!<Discontinuous mode on injected channels */\r
+                       | (0 << DISCNUM )           /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+                       | (0 << DUALMOD)             /*!<DUALMOD[3:0] bits (Dual mode selection) */\r
+                       | (0 << JAWDEN )            /*!<Analog watchdog enable on injected channels */\r
+                       | (0 << AWDEN);         /*!<Analog watchdog enable on regular channels */\r
+\r
+  ADC2->CR2 = (0 << ADON)              //           /*!<A/D Converter ON / OFF */\r
+                       | (0 << CONT)           //          /*!<Continuous Conversion */\r
+                       | (0 << CAL)                    //           /*!<A/D Calibration */\r
+                       | (0 << RSTCAL)         //            /*!<Reset Calibration */\r
+                       | (0 << DMA)                    //            /*!<Direct Memory access mode */\r
+                                                               //                              0: DMA mode disabled\r
+                                                               //                              1: DMA mode enabled\r
+                       | (0 << ALIGN)                  //            /*!<Data Alignment */\r
+                       | (0 << JEXTSEL)                //           /*!<JEXTSEL[2:0] bits (External event select for injected group) */\r
+                       | (0 << JEXTTRIG)               //           /*!<External Trigger Conversion mode for injected channels */\r
+                       | (0 << EXTSEL)         //            /*!<EXTSEL[2:0] bits (External Event Select for regular group) */\r
+                                                               //                      For ADC2 and ADC2, the assigned triggers are:\r
+                                                               //                              000: Timer 1 CC1 event\r
+                                                               //                              001: Timer 1 CC2 event\r
+                                                               //                              010: Timer 1 CC3 event\r
+                                                               //                              011: Timer 2 CC2 event\r
+                                                               //                              100: Timer 3 TRGO event\r
+                                                               //                              101: Timer 4 CC4 event\r
+                                                               //                              110: EXTI line11/TIM8_TRGO event (TIM8_TRGO is available only in high-density devices)\r
+                                                               //                              111: SWSTART\r
+                       | (0 << EXTTRIG)                //              /*!<External Trigger Conversion mode for regular channels */\r
+                       | (0 << JSWSTART)       //            /*!<Start Conversion of injected channels */\r
+                       | (0 << SWSTART)                //              /*!<Start Conversion of regular channels */\r
+                       | (0 << TSVREFE);               //              /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+ // Sample time selection\r
+ // SMPx[2:0]:\r
+ //            000: 1.5 cycles\r
+ //            001: 7.5 cycles\r
+ //            010: 13.5 cycles\r
+ //            011: 28.5 cycles\r
+ //            100: 41.5 cycles\r
+ //            101: 55.5 cycles\r
+ //            110: 71.5 cycles\r
+ //            111: 239.5 cycles\r
+ ADC2->SMPR1 = (0 << SMP10)    //           /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+                       | (0 << SMP11)  //            /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+                       | (0 << SMP12)  //              /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+                       | (0 << SMP13)  //                 /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+                       | (0 << SMP14)  //               /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+                       | (0 << SMP15)  //            /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+                       | (0 << SMP16)  //             /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+                       | (0 << SMP17);         //               /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+\r
+ ADC2->SMPR2 = (0 << SMP0 )    //        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+                       | (0 << SMP1)           //            /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+                       | (0 << SMP2)           //              /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+                       | (0 << SMP3)   //             /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+                       | (0 << SMP4 )          //              /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+                       | (0 << SMP5)           //            /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+                       | (0 << SMP6)           //           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+                       | (0 << SMP7)   //           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+                       | (0 << SMP8)   //          /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+                       | (0 << SMP9);          //            /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+  \r
+  ADC2->JOFR1 = 0x0000;\r
+  ADC2->JOFR2 = 0x0000;\r
+  ADC2->JOFR3 = 0x0000;\r
+  ADC2->JOFR4 = 0x0000;\r
+  \r
+  ADC2->HTR = 0x0FFF;\r
+  ADC2->LTR = 0x0000;\r
+\r
+ //    L[3:0]: Regular channel sequence length, i.e. number of channels in the sequence.\r
+ //            These bits are written by software to define the total number of conversions in the regular\r
+ //            channel conversion sequence.\r
+ //                    0000: 1 conversion\r
+ //                    0001: 2 conversions\r
+ //                    .....\r
+ //                    1111: 16 conversions \r
+ //    SQn[4:0]: The order of conversion in regular sequence\r
+ //            These bits are written by software with the channel number (0..17) assigned as the n-th conversion in the\r
+ //            sequence to be converted.\r
+ //\r
+ ADC2->SQR1 = (0 << SQ13 )   //            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+                       | (0 << SQ14)           //              /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+                       | (0 << SQ15)           //                /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+                       | (0 << SQ16)           //              /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+                       | (0 << L );            //             /*!<L[3:0] bits (Regular channel sequence length) */\r
+  \r
+  ADC2->SQR2 = (0 << SQ7)      //               /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+                       | (0 << SQ8)            //              /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+                       | (0 << SQ9)            //                /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+                       | (0 << SQ10)           //               /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+                       | (0 << SQ11)           //               /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+                       | (0 << SQ12);          //               /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+  \r
+  ADC2->SQR3 = (0 << SQ1)      //             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+                       | (0 << SQ2)            //            /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+                       | (0 << SQ3)            //              /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+                       | (0 << SQ4)            //             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+                       | (0 << SQ5)            //              /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+                       | (0 << SQ6);           //             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+                       \r
+ //    JL[1:0]: Injected sequence length\r
+ //            These bits are written by software to define the total number of conversions in the injected\r
+ //            channel conversion sequence.\r
+ //                    00: 1 conversion\r
+ //                    01: 2 conversions\r
+ //                    10: 3 conversions\r
+ //                    11: 4 conversions\r
+ //    JSQ4[4:0]: 4th conversion in injected sequence\r
+ //            These bits are written by software with the channel number (0..17) assigned as the 4th in\r
+ //            the sequence to be converted.\r
+ //            Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels\r
+ //                            are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10\r
+ //                            00011 00011 00111 00010 means that a scan conversion will convert the following\r
+ //                            channel sequence: 7, 3, 3. (not 2, 7, 3) \r
+ //\r
+  ADC2->JSQR = (0 << JSQ1)     //            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  \r
+                       | (0 << JSQ2)           //             /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+                       | (0 << JSQ3)           //             /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+                       | (0 << JSQ4)           //              /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+                       | (0 << JL);            //            /*!<JL[1:0] bits (Injected Sequence length) */\r
+\r
+  // These registers are read-only\r
+//  ADC2->JDR1;\r
+//  ADC2->JDR2;\r
+//  ADC2->JDR3;\r
+//  ADC2->JDR4;\r
+//  ADC2->DR;\r
+\r
+ // Do calibration\r
+ ADC2->CR2 |= (1 << CAL);              \r
+ while(!BitTest(ADC2->CR2, (1 << CAL))) {\r
+       // Wait for end of  calibration\r
+       }\r
\r
+ // Start ADC (the first ADON set turn on ADC power)\r
+ ADC2->CR2 |= (1 << ADON);             //           /*!<A/D Converter ON / OFF */\r
+}\r
+\r
+\r
+U16    ADC_Poll(ADC_TypeDef * adc, U8 chn)\r
+{\r
+ // Assuming that the ADC refered has been properly initialized with channel and sample time selected.\r
+  adc->SQR3 = (chn << SQ1);            //             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
\r
+ // Start conversion\r
+ adc->CR2 |= (1 << ADON); \r
+ while(!BitTest(adc->SR, (1 << EOC))) {\r
+       // Wait for end of conversion\r
+       }\r
+ return (adc->DR);\r
+}\r
+\r
+void   TFT_Init_Ili9341(void)\r
+{\r
+ U8  tmp;\r
+\r
+ // Reset TFT controller (Ili9341)\r
+ SetToHigh(TFT_nRESET_Port, (1 << TFT_nRESET_Bit));\r
+ Delay(5000);  // About 1.1ms\r
+ SetToLow(TFT_nRESET_Port, (1 << TFT_nRESET_Bit));\r
+ Delay(65000); // About 15ms\r
+ SetToHigh(TFT_nRESET_Port, (1 << TFT_nRESET_Bit));\r
+ tmp = 10;\r
+ while(tmp) {\r
+       Delay(65535);\r
+       tmp--;\r
+       }\r
\r
+       write_comm(0xcf); \r
+       write_data(0x00);\r
+       write_data(0xC1);\r
+       write_data(0x30);\r
+\r
+       write_comm(0xed); \r
+       write_data(0x67);\r
+       write_data(0x03);\r
+       write_data(0x12);\r
+       write_data(0x81);\r
+\r
+       write_comm(0xcb); \r
+       write_data(0x39);\r
+       write_data(0x2c);\r
+       write_data(0x00);\r
+       write_data(0x34);\r
+       write_data(0x02);\r
+\r
+       write_comm(0xea); \r
+       write_data(0x00);\r
+       write_data(0x00);\r
+\r
+       write_comm(0xe8); \r
+       write_data(0x85);\r
+       write_data(0x0a);\r
+       write_data(0x78);\r
+\r
+       write_comm(0xF7); \r
+       write_data(0x20);\r
+\r
+       write_comm(0xC0); //Power control\r
+       write_data(0x26); //VRH[5:0]\r
+\r
+       write_comm(0xC1); //Power control\r
+       write_data(0x01); //SAP[2:0];BT[3:0]\r
+\r
+       write_comm(0xC5); //VCM control\r
+       write_data(0x2b);\r
+       write_data(0x2F);\r
+\r
+       write_comm(0xc7); \r
+       write_data(0xc7);\r
+\r
+       write_comm(0x3A); \r
+       write_data(0x55);\r
+\r
+       write_comm(0x36); // Memory Access Control\r
+//     write_data(0x08);\r
+       write_data(0x20);\r
+       \r
+       write_comm(0xB1); // Frame Rate Control\r
+       write_data(0x00);\r
+       write_data(0x18);\r
+       \r
+       write_comm(0xB6); // Display Function Control\r
+       write_data(0x0a);\r
+       write_data(0xE2);\r
+       \r
+       write_comm(0xF2); // 3Gamma Function Disable\r
+       write_data(0x00);\r
+       write_comm(0x26); //Gamma curve selected\r
+       write_data(0x01);\r
+       write_comm(0xE0); //Set Gamma\r
+       write_data(0x0f);\r
+       write_data(0x1d);\r
+       write_data(0x1a);\r
+       write_data(0x09);\r
+       write_data(0x0f);\r
+       write_data(0x09);\r
+       write_data(0x46);\r
+       write_data(0x88);\r
+       write_data(0x39);\r
+       write_data(0x05);\r
+       write_data(0x0f);\r
+       write_data(0x03);\r
+       write_data(0x07);\r
+       write_data(0x05);\r
+       write_data(0x00);\r
+\r
+       write_comm(0XE1); //Set Gamma\r
+       write_data(0x00);\r
+       write_data(0x22);\r
+       write_data(0x25);\r
+       write_data(0x06);\r
+       write_data(0x10);\r
+       write_data(0x06);\r
+       write_data(0x39);\r
+       write_data(0x22);\r
+       write_data(0x4a);\r
+       write_data(0x0a);\r
+       write_data(0x10);\r
+       write_data(0x0c);\r
+       write_data(0x38);\r
+       write_data(0x3a);\r
+       write_data(0x0F);\r
+\r
+       write_comm(0x11); //Exit Sleep\r
+//     delay(120);\r
+        tmp = 100;\r
+        while(tmp) {\r
+               Delay(50000);\r
+               tmp--;\r
+               }\r
+       write_comm(0x29); //display on  \r
+//     write_comm(0x2C);       \r
+\r
+ Delay(50000);\r
+ Delay(50000);\r
\r
+}\r
+\r
+\r
+void   write_comm(U8 commport)\r
+{\r
+ // Set TFT_nCS low\r
+ SetToLow(TFT_nCS_Port, (1 << TFT_nCS_Bit));\r
+ // Set up to access Index Register (RS == 0)\r
+ SetToLow(TFT_RS_Port, (1 << TFT_RS_Bit));\r
+// Delay(2);\r
+\r
+ TFT_Port = (TFT_Port & 0xFF00) | commport;\r
+ SetToLow(TFT_nWR_Port, (1 << TFT_nWR_Bit));\r
+ SetToHigh(TFT_nWR_Port, (1 << TFT_nWR_Bit));\r
+\r
+ // Set up to access Data Register (RS == 1)\r
+ SetToHigh(TFT_RS_Port, (1 << TFT_RS_Bit));\r
+// Delay(2);\r
+\r
+ // Set TFT_nCS high\r
+ SetToHigh(TFT_nCS_Port, (1 << TFT_nCS_Bit));\r
\r
+}\r
+\r
+void write_data(U8 data)\r
+{\r
+ // Set TFT_nCS low\r
+ SetToLow(TFT_nCS_Port, (1 << TFT_nCS_Bit));\r
+\r
+ // Set up to access Data Register (RS == 1)\r
+ SetToHigh(TFT_RS_Port, (1 << TFT_RS_Bit));\r
+\r
+ TFT_Port = (TFT_Port & 0xFF00) | data;\r
+ SetToLow(TFT_nWR_Port, (1 << TFT_nWR_Bit));\r
+ SetToHigh(TFT_nWR_Port, (1 << TFT_nWR_Bit));\r
+\r
+ // Set TFT_nCS high\r
+ SetToHigh(TFT_nCS_Port, (1 << TFT_nCS_Bit));\r
\r
+}\r
+\r
+\r
+void assert_failed(U8 * file, U32 line)\r
+//void assert_failed((U8 *) file, U32 line)\r
+{\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures the nested vectored interrupt controller.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void NVIC_Configuration(void)\r
+{\r
+  NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+// NVIC_SetVectorTable(NVIC_VectTab_RAM, 0);\r
+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0);\r
+\r
+\r
+  // Enable the TIM1 Interrupt \r
+  NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn;\r
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+  NVIC_Init(&NVIC_InitStructure); \r
+\r
+\r
+  // Enable the ADC1 Interrupt \r
+  NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;\r
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+  NVIC_Init(&NVIC_InitStructure); \r
\r
+  // Enable the DMA1 channel1 Interrupt \r
+  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn;\r
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+  NVIC_Init(&NVIC_InitStructure);\r
+\r
+}\r
+\r
+\r
+void   OutputTLvl(void)\r
+{\r
+ TIM4->CCR3 = GetTrigLvl() + GetVPosOfs() + 0x800;\r
+}\r
+\r
+\r
diff --git a/Board.h b/Board.h
new file mode 100644 (file)
index 0000000..6153abd
--- /dev/null
+++ b/Board.h
@@ -0,0 +1,808 @@
+//////////////////////////////////////////////////////////////////////////////\r
+//\r
+//     Filename:       Board.h\r
+//     Version:                \r
+//     Data:           \r
+//\r
+//     Author:         Liu, Zemin
+//     Company:        JYE Tech Ltd.\r
+//     Web:            www.jyetech.com\r
+//
+//-----------------------------------------------------------------------------
+//
+//     Target:                 STM32F103C8\r
+//     Tool chain:     CodeSourcery G++\r
+//
+//-----------------------------------------------------------------------------\r
+//     Required files:\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Notes:\r
+//\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Revision History:\r
+//\r
+///////////////////////////////////////////////////////////////////////////////\r
+//\r
+//\r
+\r
+#ifndef        Board_h\r
+\r
+#define        Board_h\r
+\r
+#include       "Common.h"\r
+\r
+#include "stm32f10x.h"\r
+//#include "stm32f10x_conf.h"\r
+\r
+// TFT control ports\r
+\r
+#define        TFT_nRESET_Port                 GPIOB   \r
+#define        TFT_nRESET_Bit                          11              \r
+#define        TFT_RS_Port                                     GPIOC\r
+#define        TFT_RS_Bit                                      14      \r
+#define        TFT_nCS_Port                            GPIOC\r
+#define        TFT_nCS_Bit                                     13      \r
+#define        TFT_nWR_Port                            GPIOC\r
+#define        TFT_nWR_Bit                             15      \r
+#define        TFT_nRD_Port                            GPIOB\r
+#define        TFT_nRD_Bit                                     10      \r
+\r
+#define        TFT_Port                                        (GPIOB->ODR)\r
+\r
+#define        LED_Base                                        GPIOA\r
+#define        LED_Port                                        (GPIOA->ODR)\r
+#define        LED_Bit                                         15\r
+\r
+// Pushbuttons\r
+#define        PB_Port                                         (GPIOB->IDR)\r
+#define        PB_Bits                                         0xF000\r
+\r
+\r
+// ======== STM32 Register Constants =====================\r
+\r
+// -------- Register address -----------------\r
+// RCC registers\r
+#define RCC_AHBENR (*((unsigned int *)(0x40021014)))\r
+#define RCC_APB2ENR (*((unsigned int *)(0x40021018)))\r
+#define RCC_APB1ENR (*((unsigned int *)(0x4002101C)))\r
+\r
+// GPIO registers\r
+#define GPIOA_CRL   (*((unsigned int *)(0x40010800)))\r
+#define GPIOA_BSRR  (*((unsigned int *)(0x40010810)))\r
+#define GPIOA_BRR   (*((unsigned int *)(0x40010814)))\r
+\r
+#define GPIOB_CRL   (*((unsigned int *)(0x40010C00)))\r
+#define GPIOB_CRH   (*((unsigned int *)(0x40010C04)))\r
+#define GPIOB_IDR   (*((unsigned int *)(0x40010C08)))\r
+#define GPIOB_ODR   (*((unsigned int *)(0x40010C0C)))\r
+#define GPIOB_BSRR  (*((unsigned int *)(0x40010C10)))\r
+#define GPIOB_BRR   (*((unsigned int *)(0x40010C14)))\r
+#define GPIOB_LCKR   (*((unsigned int *)(0x40010C18)))\r
+\r
+#define GPIOD_CRL   (*((unsigned int *)(0x40011400)))\r
+#define GPIOD_CRH   (*((unsigned int *)(0x40011404)))\r
+#define GPIOD_IDR   (*((unsigned int *)(0x40011408)))\r
+#define GPIOD_ODR   (*((unsigned int *)(0x4001140C)))\r
+#define GPIOD_BSRR  (*((unsigned int *)(0x40011410)))\r
+#define GPIOD_BRR   (*((unsigned int *)(0x40011414)))\r
+#define GPIOD_LCKR   (*((unsigned int *)(0x40011418)))\r
+\r
+#define GPIOE_CRL   (*((unsigned int *)(0x40011800)))\r
+#define GPIOE_CRH   (*((unsigned int *)(0x40011804)))\r
+#define GPIOE_IDR   (*((unsigned int *)(0x40011808)))\r
+#define GPIOE_ODR   (*((unsigned int *)(0x4001180C)))\r
+#define GPIOE_BSRR  (*((unsigned int *)(0x40011810)))\r
+#define GPIOE_BRR   (*((unsigned int *)(0x40011814)))\r
+#define GPIOE_LCKR   (*((unsigned int *)(0x40011818)))\r
+\r
+// FSMC registers\r
+#define FSMC_BCR1   (*((U32 *)(0xA0000000)))\r
+#define FSMC_BTR1   (*((U32 *)(0xA0000004)))\r
+#define FSMC_BWTR1   (*((U32  *)(0xA0000104)))\r
+\r
+#define FSMC_BCR2   (*((U32  *)(0xA0000008)))\r
+#define FSMC_BTR2   (*((U32  *)(0xA000000C)))\r
+#define FSMC_BWTR2   (*((U32  *)(0xA000010C)))\r
+\r
+// ---------------- Bit fields ------------------------\r
+// Clock control\r
+//-- AHBENR\r
+#define        SDIOEN                  10\r
+#define        FSMCEN                  8\r
+#define        CRCEN                   6\r
+#define        FLITFEN                 4\r
+#define        SRAMEN                  2\r
+#define        DMA2EN                  1\r
+#define        DMA1EN                  0\r
+\r
+//-- APB1ENR\r
+#define        DACEN                   29\r
+#define        PWREN                   28\r
+#define        BKPEN                   27\r
+#define        CANEN                   25\r
+#define        USBEN                   23\r
+#define        I2C2EN                  22\r
+#define        I2C1EN                  21\r
+#define        UART5EN         20\r
+#define        UART4EN         19\r
+#define        USART3EN                18\r
+#define        USART2EN                17\r
+\r
+#define        SPI3EN                  15\r
+#define        SPI2EN                  14\r
+#define        WWDGEN          11\r
+#define        TIM7EN                  5\r
+#define        TIM6EN                  4\r
+#define        TIM5EN                  3\r
+#define        TIM4EN                  2\r
+#define        TIM3EN                  1\r
+#define        TIM2EN                  0\r
+\r
+//-- APB2ENR\r
+#define        ADC3EN                  15\r
+#define        USART1EN                14\r
+#define        TIM8EN                  13\r
+#define        SPI1EN                  12\r
+#define        TIM1EN                  11\r
+#define        ADC2EN                  10\r
+#define        ADC1EN                  9\r
+#define        IOPGEN                  8\r
+#define        IOPFEN                  7\r
+#define        IOPEEN                  6\r
+#define        IOPDEN                  5\r
+#define        IOPCEN                  4\r
+#define        IOPBEN                  3\r
+#define        IOPAEN                  2\r
+#define        AFIOEN                  0\r
+\r
+\r
+// ---------------- Bit fields ------------------------\r
+// Clock control\r
+//\r
+/********************  Bit definition for RCC_CR register  ********************/\r
+#define  HSION                 0               /*!< Internal High Speed clock enable */\r
+#define  HSIRDY                1               /*!< Internal High Speed clock ready flag */\r
+#define  HSITRIM               3               /*!< Internal High Speed clock trimming */\r
+#define  HSICAL                8               /*!< Internal High Speed clock Calibration */\r
+#define  HSEON                 16              /*!< External High Speed clock enable */\r
+#define  HSERDY                17              /*!< External High Speed clock ready flag */\r
+#define  HSEBYP                18              /*!< External High Speed clock Bypass */\r
+#define  CSSON                         19              /*!< Clock Security System enable */\r
+#define  PLLON                 24              /*!< PLL enable */\r
+#define  PLLRDY                        25              /*!< PLL clock ready flag */\r
+\r
+/*******************  Bit definition for RCC_CFGR register  *******************/\r
+/*!< SW configuration */\r
+#define  SW                    0               /*!< SW[1:0] bits (System clock Switch) */\r
+\r
+/*!< SWS configuration */\r
+#define  SWS                   2               /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+\r
+/*!< HPRE configuration */\r
+#define  HPRE                          4               /*!< HPRE[3:0] bits (AHB prescaler) */\r
+\r
+/*!< PPRE1 configuration */\r
+#define  PPRE1                         8               /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+\r
+/*!< PPRE2 configuration */\r
+#define  PPRE2                         11              /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+\r
+/*!< ADCPPRE configuration */\r
+#define  ADCPRE                        14              /*!< ADCPRE[1:0] bits (ADC prescaler) */\r
+\r
+#define  PLLSRC                        16              /*!< PLL entry clock source */\r
+\r
+#define  PLLXTPRE              17               /*!< HSE divider for PLL entry */\r
+\r
+/*!< PLLMUL configuration */\r
+#define  PLLMULL               18              /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+\r
+ #define  USBPRE               22              /*!< USB Device prescaler */\r
+\r
+/*!< MCO configuration */\r
+#define  MCO                           24              /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+\r
+/*!<******************  Bit definition for RCC_CIR register  ********************/\r
+#define  LSIRDYF               0                /*!< LSI Ready Interrupt flag */\r
+#define  LSERDYF               1               /*!< LSE Ready Interrupt flag */\r
+#define  HSIRDYF               2               /*!< HSI Ready Interrupt flag */\r
+#define  HSERDYF               3               /*!< HSE Ready Interrupt flag */\r
+#define  PLLRDYF               4               /*!< PLL Ready Interrupt flag */\r
+#define  CSSF                          7               /*!< Clock Security System Interrupt flag */\r
+#define  LSIRDYIE              8                /*!< LSI Ready Interrupt Enable */\r
+#define  LSERDYIE              9               /*!< LSE Ready Interrupt Enable */\r
+#define  HSIRDYIE              10              /*!< HSI Ready Interrupt Enable */\r
+#define  HSERDYIE              11              /*!< HSE Ready Interrupt Enable */\r
+#define  PLLRDYIE              12              /*!< PLL Ready Interrupt Enable */\r
+#define  LSIRDYC               16              /*!< LSI Ready Interrupt Clear */\r
+#define  LSERDYC               17              /*!< LSE Ready Interrupt Clear */\r
+#define  HSIRDYC               18              /*!< HSI Ready Interrupt Clear */\r
+#define  HSERDYC               19              /*!< HSE Ready Interrupt Clear */\r
+#define  PLLRDYC               20              /*!< PLL Ready Interrupt Clear */\r
+#define  CSSC                          23              /*!< Clock Security System Interrupt Clear */\r
+\r
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/\r
+#define  AFIORST               0               /*!< Alternate Function I/O reset */\r
+#define  IOPARST               2               /*!< I/O port A reset */\r
+#define  IOPBRST               3               /*!< I/O port B reset */\r
+#define  IOPCRST               4               /*!< I/O port C reset */\r
+#define  IOPDRST               5                /*!< I/O port D reset */\r
+#define  IOPERST               6               /*!< I/O port E reset */\r
+#define  IOPFRST               7               /*!< I/O port F reset */\r
+#define  IOPGRST               8               /*!< I/O port G reset */\r
+#define  ADC1RST               9               /*!< ADC 1 interface reset */\r
+#define  ADC2RST               10              /*!< ADC 2 interface reset */\r
+#define  TIM1RST               11              /*!< TIM1 Timer reset */\r
+#define  SPI1RST               12              /*!< SPI 1 reset */\r
+#define  TIM8RST               13              /*!< TIM8 Timer reset */\r
+#define  USART1RST             14              /*!< USART1 reset */\r
+#define  ADC3RST               15              /*!< ADC3 interface reset */\r
+\r
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/\r
+#define  TIM2RST               0               /*!< Timer 2 reset */\r
+#define  TIM3RST               1               /*!< Timer 3 reset */\r
+#define  TIM4RST               2               /*!< Timer 4 reset */\r
+#define  TIM5RST               3               /*!< Timer 5 reset */\r
+#define  TIM6RST               4                /*!< Timer 6 reset */\r
+#define  TIM7RST               5               /*!< Timer 7 reset */\r
+#define  WWDGRST               11              /*!< Window Watchdog reset */\r
+#define  SPI2RST               14              /*!< SPI 2 reset */\r
+#define  SPI3RST               15              /*!< SPI 3 reset */\r
+#define  USART2RST             17              /*!< USART 2 reset */\r
+#define  USART3RST             18              /*!< RUSART 3 reset */\r
+#define  UART4RST              19              /*!< UART 4 reset */\r
+#define  UART5RST              20              /*!< UART 5 reset */\r
+#define  I2C1RST               21              /*!< I2C 1 reset */\r
+#define  I2C2RST               22              /*!< I2C 2 reset */\r
+#define  USBRST                23              /*!< USB Device reset */\r
+#define  CAN1RST               25              /*!< CAN1 reset */\r
+#define  BKPRST                27              /*!< Backup interface reset */\r
+#define  PWRRST                28              /*!< Power interface reset */\r
+#define  DACRST                29              /*!< DAC interface reset */\r
+\r
+/******************  Bit definition for RCC_AHBENR register  ******************/\r
+#define  DMA1EN                0               /*!< DMA1 clock enable */\r
+#define  DMA2EN                1               /*!< DMA2 clock enable */\r
+#define  SRAMEN                2                /*!< SRAM interface clock enable */\r
+#define  FLITFEN                       4               /*!< FLITF clock enable */\r
+#define  CRCEN                 6               /*!< CRC clock enable */\r
+#define  FSMCEN                8               /*!< FSMC clock enable */\r
+#define  SDIOEN                10              /*!< SDIO clock enable */\r
+\r
+/******************  Bit definition for RCC_APB2ENR register  *****************/\r
+#define  AFIOEN                 0              /*!< Alternate Function I/O clock enable */\r
+#define  IOPAEN                2               /*!< I/O port A clock enable */\r
+#define  IOPBEN                3               /*!< I/O port B clock enable */\r
+#define  IOPCEN                4               /*!< I/O port C clock enable */\r
+#define  IOPDEN                5               /*!< I/O port D clock enable */\r
+#define  IOPEEN                        6               /*!< I/O port E clock enable */\r
+#define  IOPFEN                7               /*!< I/O port F clock enable */\r
+#define  IOPGEN                8               /*!< I/O port G clock enable */\r
+#define  ADC1EN                        9               /*!< ADC 1 interface clock enable */\r
+#define  ADC2EN                        10              /*!< ADC 2 interface clock enable */\r
+#define  TIM1EN                11              /*!< TIM1 Timer clock enable */\r
+#define  SPI1EN                        12              /*!< SPI 1 clock enable */\r
+#define  TIM8EN                13              /*!< TIM8 Timer clock enable */\r
+#define  USART1EN              14              /*!< USART1 clock enable */\r
+#define  ADC3EN                15              /*!< DMA1 clock enable */\r
+\r
+/*****************  Bit definition for RCC_APB1ENR register  ******************/\r
+#define  TIM2EN                        0               /*!< Timer 2 clock enabled*/\r
+#define  TIM3EN                        1               /*!< Timer 3 clock enable */\r
+#define  TIM4EN                2               /*!< Timer 4 clock enable */\r
+#define  TIM5EN                3               /*!< Timer 5 clock enable */\r
+#define  TIM6EN                4               /*!< Timer 6 clock enable */\r
+#define  TIM7EN                5               /*!< Timer 7 clock enable */\r
+#define  WWDGEN                11              /*!< Window Watchdog clock enable */\r
+#define  SPI2EN                14              /*!< SPI 2 clock enable */\r
+#define  SPI3EN                        15              /*!< SPI 3 clock enable */\r
+#define  USART2EN              17              /*!< USART 2 clock enable */\r
+#define  USART3EN              18              /*!< USART 3 clock enable */\r
+#define  UART4EN               19              /*!< UART 4 clock enable */\r
+#define  UART5EN               20              /*!< UART 5 clock enable */\r
+#define  I2C1EN                        21              /*!< I2C 1 clock enable */\r
+#define  I2C2EN                22              /*!< I2C 2 clock enable */\r
+#define  USBEN                 23              /*!< USB Device clock enable */\r
+#define  CAN1EN                        25              /*!< CAN1 clock enable */\r
+#define  BKPEN                         27              /*!< Backup interface clock enable */\r
+#define  PWREN                 28              /*!< Power interface clock enable */\r
+#define  DACEN                         29              /*!< DAC interface clock enable */\r
+\r
+\r
+/*******************  Bit definition for RCC_BDCR register  *******************/\r
+#define  LSEON                 0               /*!< External Low Speed oscillator enable */\r
+#define  LSERDY                1               /*!< External Low Speed oscillator Ready */\r
+#define  LSEBYP                2               /*!< External Low Speed oscillator Bypass */\r
+\r
+#define  RTCSEL                        8               /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+\r
+#define  RTCEN                   15            /*!< RTC clock enable */\r
+#define  BDRST                 16              /*!< Backup domain software reset  */\r
+\r
+/*******************  Bit definition for RCC_CSR register  ********************/  \r
+#define  LSION                         0               /*!< Internal Low Speed oscillator enable */\r
+#define  LSIRDY                1               /*!< Internal Low Speed oscillator Ready */\r
+#define  RMVF                          24              /*!< Remove reset flag */\r
+#define  PINRSTF               26              /*!< PIN reset flag */\r
+#define  PORRSTF               27              /*!< POR/PDR reset flag */\r
+#define  SFTRSTF               28              /*!< Software Reset flag */\r
+#define  IWDGRSTF            29                /*!< Independent Watchdog reset flag */\r
+#define  WWDGRSTF              30              /*!< Window watchdog reset flag */\r
+#define  LPWRRSTF              31              /*!< Low-Power reset flag */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    TIM                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for TIM_CR1 register  ********************/\r
+#define  CEN                           0           /*!<Counter enable */\r
+#define  UDIS                          1            /*!<Update disable */\r
+#define  URS                           2            /*!<Update request source */\r
+#define  OPM                           3            /*!<One pulse mode */\r
+#define  DIR                           4            /*!<Direction */\r
+\r
+#define  CMS                           5            /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+\r
+#define  ARPE                          7            /*!<Auto-reload preload enable */\r
+\r
+#define  CKD                           8            /*!<CKD[1:0] bits (clock division) */\r
+\r
+/*******************  Bit definition for TIM_CR2 register  ********************/\r
+#define  CCPC                  0           /*!<Capture/Compare Preloaded Control */\r
+#define  CCUS                          2            /*!<Capture/Compare Control Update Selection */\r
+#define  CCDS                  3           /*!<Capture/Compare DMA Selection */\r
+\r
+#define  MMS                           4            /*!<MMS[2:0] bits (Master Mode Selection) */\r
+\r
+#define  TI1S                  7           /*!<TI1 Selection */\r
+#define  OIS1                          8           /*!<Output Idle state 1 (OC1 output) */\r
+#define  OIS1N                 9            /*!<Output Idle state 1 (OC1N output) */\r
+#define  OIS2                  10           /*!<Output Idle state 2 (OC2 output) */\r
+#define  OIS2N                         11           /*!<Output Idle state 2 (OC2N output) */\r
+#define  OIS3                          12            /*!<Output Idle state 3 (OC3 output) */\r
+#define  OIS3N                         13            /*!<Output Idle state 3 (OC3N output) */\r
+#define  OIS4                          14           /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/*******************  Bit definition for TIM_SMCR register  *******************/\r
+#define  SMS                           0            /*!<SMS[2:0] bits (Slave mode selection) */\r
+\r
+#define  TS                            4            /*!<TS[2:0] bits (Trigger selection) */\r
+\r
+#define  MSM                           7            /*!<Master/slave mode */\r
+\r
+#define  ETF                           8           /*!<ETF[3:0] bits (External trigger filter) */\r
+\r
+#define  ETPS                          12           /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+\r
+#define  ECE                           14            /*!<External clock enable */\r
+#define  ETP                           15           /*!<External trigger polarity */\r
+\r
+/*******************  Bit definition for TIM_DIER register  *******************/\r
+#define  UIE                           0           /*!<Update interrupt enable */\r
+#define  CC1IE                         1           /*!<Capture/Compare 1 interrupt enable */\r
+#define  CC2IE                         2           /*!<Capture/Compare 2 interrupt enable */\r
+#define  CC3IE                         3           /*!<Capture/Compare 3 interrupt enable */\r
+#define  CC4IE                         4           /*!<Capture/Compare 4 interrupt enable */\r
+#define  COMIE                         5           /*!<COM interrupt enable */\r
+#define  TIE                           6            /*!<Trigger interrupt enable */\r
+#define  BIE                           7           /*!<Break interrupt enable */\r
+#define  UDE                           8           /*!<Update DMA request enable */\r
+#define  CC1DE                 9            /*!<Capture/Compare 1 DMA request enable */\r
+#define  CC2DE                         10           /*!<Capture/Compare 2 DMA request enable */\r
+#define  CC3DE                         11           /*!<Capture/Compare 3 DMA request enable */\r
+#define  CC4DE                         12           /*!<Capture/Compare 4 DMA request enable */\r
+#define  COMDE                 13           /*!<COM DMA request enable */\r
+#define  TDE                           14           /*!<Trigger DMA request enable */\r
+\r
+/********************  Bit definition for TIM_SR register  ********************/\r
+#define  UIF                           0           /*!<Update interrupt Flag */\r
+#define  CC1IF                         1           /*!<Capture/Compare 1 interrupt Flag */\r
+#define  CC2IF                         2            /*!<Capture/Compare 2 interrupt Flag */\r
+#define  CC3IF                         3           /*!<Capture/Compare 3 interrupt Flag */\r
+#define  CC4IF                         4           /*!<Capture/Compare 4 interrupt Flag */\r
+#define  COMIF                 5           /*!<COM interrupt Flag */\r
+#define  TIF                           6           /*!<Trigger interrupt Flag */\r
+#define  BIF                           7          /*!<Break interrupt Flag */\r
+#define  CC1OF                         9           /*!<Capture/Compare 1 Overcapture Flag */\r
+#define  CC2OF                         10           /*!<Capture/Compare 2 Overcapture Flag */\r
+#define  CC3OF                         11         /*!<Capture/Compare 3 Overcapture Flag */\r
+#define  CC4OF                         12           /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/*******************  Bit definition for TIM_EGR register  ********************/\r
+#define  UG                            0              /*!<Update Generation */\r
+#define  CC1G                          1               /*!<Capture/Compare 1 Generation */\r
+#define  CC2G                          2              /*!<Capture/Compare 2 Generation */\r
+#define  CC3G                          3               /*!<Capture/Compare 3 Generation */\r
+#define  CC4G                          4             /*!<Capture/Compare 4 Generation */\r
+#define  COMG                          5             /*!<Capture/Compare Control Update Generation */\r
+#define  TG                            6             /*!<Trigger Generation */\r
+#define  BG                            7              /*!<Break Generation */\r
+\r
+/******************  Bit definition for TIM_CCMR1 register  *******************/\r
+#define  CC1S                          0           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+\r
+#define  OC1FE                         2           /*!<Output Compare 1 Fast enable */\r
+#define  OC1PE                         3           /*!<Output Compare 1 Preload enable */\r
+\r
+#define  OC1M                          4           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+\r
+#define  OC1CE                         7           /*!<Output Compare 1Clear Enable */\r
+\r
+#define  CC2S                          8           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+\r
+#define  OC2FE                 10           /*!<Output Compare 2 Fast enable */\r
+#define  OC2PE                         11           /*!<Output Compare 2 Preload enable */\r
+\r
+#define  OC2M                          12            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+\r
+#define  OC2CE                         15           /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define  IC1PSC                2           /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+\r
+#define  IC1F                          4           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+\r
+#define  IC2PSC                        10          /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+\r
+#define  IC2F                          12           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+\r
+/******************  Bit definition for TIM_CCMR2 register  *******************/\r
+#define  CC3S                          0           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+\r
+#define  OC3FE                         2           /*!<Output Compare 3 Fast enable */\r
+#define  OC3PE                         3          /*!<Output Compare 3 Preload enable */\r
+\r
+#define  OC3M                          4           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+\r
+#define  OC3CE                         7           /*!<Output Compare 3 Clear Enable */\r
+\r
+#define  CC4S                          8           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+\r
+#define  OC4FE                         10           /*!<Output Compare 4 Fast enable */\r
+#define  OC4PE                         11           /*!<Output Compare 4 Preload enable */\r
+\r
+#define  OC4M                          12           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+\r
+#define  OC4CE                         15           /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define  IC3PSC                2           /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+\r
+#define  IC3F                          4          /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+\r
+#define  IC4PSC                        10           /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+\r
+#define  IC4F                          12           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+\r
+/*******************  Bit definition for TIM_CCER register  *******************/\r
+#define  CC1E                     0         /*!<Capture/Compare 1 output enable */\r
+#define  CC1P                          1          /*!<Capture/Compare 1 output Polarity */\r
+#define  CC1NE                         2           /*!<Capture/Compare 1 Complementary output enable */\r
+#define  CC1NP                         3           /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define  CC2E                          4           /*!<Capture/Compare 2 output enable */\r
+#define  CC2P                          5            /*!<Capture/Compare 2 output Polarity */\r
+#define  CC2NE                 6            /*!<Capture/Compare 2 Complementary output enable */\r
+#define  CC2NP                         7           /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define  CC3E                          8          /*!<Capture/Compare 3 output enable */\r
+#define  CC3P                          9           /*!<Capture/Compare 3 output Polarity */\r
+#define  CC3NE                 10          /*!<Capture/Compare 3 Complementary output enable */\r
+#define  CC3NP                         11           /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define  CC4E                          12          /*!<Capture/Compare 4 output enable */\r
+#define  CC4P                          13           /*!<Capture/Compare 4 output Polarity */\r
+\r
+/*******************  Bit definition for TIM_BDTR register  *******************/\r
+#define  DTG                           0           /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+\r
+#define  LOCK                          8           /*!<LOCK[1:0] bits (Lock Configuration) */\r
+\r
+#define  OSSI                          10           /*!<Off-State Selection for Idle mode */\r
+#define  OSSR                          11          /*!<Off-State Selection for Run mode */\r
+#define  BKE                           12          /*!<Break enable */\r
+//#define  BKP                         13          /*!<Break Polarity */\r
+#define  AOE                           14           /*!<Automatic Output enable */\r
+#define  MOE                           15           /*!<Main Output enable */\r
+\r
+/*******************  Bit definition for TIM_DCR register  ********************/\r
+#define  DBA                           0           /*!<DBA[4:0] bits (DMA Base Address) */\r
+\r
+#define  DBL                       8            /*!<DBL[4:0] bits (DMA Burst Length) */\r
+\r
+/*******************  Bit definition for TIM_DMAR register  *******************/\r
+#define  DMAB                          0          /*!<DMA register for burst accesses */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                               SystemTick                                   */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*****************  Bit definition for SysTick_CTRL register  *****************/\r
+#define  SysTick_ENABLE                0       //      ((uint32_t)0x00000001)        /*!< Counter enable */\r
+#define  SysTick_TICKINT               1       //    ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */\r
+#define  SysTick_CLKSOURCE             2       //        ((uint32_t)0x00000004)        /*!< Clock source */\r
+#define  SysTick_COUNTFLAG             16      //       ((uint32_t)0x00010000)        /*!< Count Flag */\r
+\r
+/*****************  Bit definition for SysTick_LOAD register  *****************/\r
+#define  SysTick_RELOAD                0       //   ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/*****************  Bit definition for SysTick_VAL register  ******************/\r
+#define  SysTick_CURRENT               0       //      ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */\r
+\r
+/*****************  Bit definition for SysTick_CALIB register  ****************/\r
+#define  SysTick_TENMS                 0       //  ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */\r
+#define  SysTick_SKEW                  30      //   ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */\r
+#define  SysTick_NOREF                 31      // ((uint32_t)0x80000000)        /*!< The reference clock is not provided */\r
+\r
+// GPIO port configuration constants\r
+#define        GPIO_Mode_In                            0x00\r
+#define        GPIO_Mode_Out10M                        0x01\r
+#define        GPIO_Mode_Out2M                 0x02\r
+#define        GPIO_Mode_Out50M                        0x03\r
+\r
+#define        GPIO_CNF_GP_PP                  0x00\r
+#define        GPIO_CNF_GP_OD                  0x04\r
+#define        GPIO_CNF_AF_PP                  0x08\r
+#define        GPIO_CNF_AF_OD                  0x0C\r
+#define        GPIO_CNF_AnalogIn                       0x00\r
+#define        GPIO_CNF_Floating                       0x04\r
+#define        GPIO_CNF_IPD                            0x08\r
+#define        GPIO_CNF_IPU                            0x08\r
+\r
+/******************  Bit definition for FSMC_BCR registers  *******************/\r
+#define  CBURSTRW              16        /*!<Write burst enable */\r
+#define  EXTMOD                14        /*!<Extended mode enable */\r
+#define  WAITEN                13        /*!<Wait enable bit */\r
+#define  WREN                          12        /*!<Write enable bit */\r
+#define  WAITCFG               11        /*!<Wait timing configuration */\r
+#define  WRAPMOD               10        /*!<Wrapped burst mode support */\r
+#define  WAITPOL              9        /*!<Wait signal polarity bit */\r
+#define  BURSTEN               8        /*!<Burst enable bit */\r
+#define  FACCEN                6        /*!<Flash access enable */\r
+#define  MWID                          4        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  MTYP                          2        /*!<MTYP[1:0] bits (Memory type) */\r
+#define  MUXEN                         1        /*!<Address/data multiplexing enable bit */\r
+#define  MBKEN                 0        /*!<Memory bank enable bit */\r
+\r
+/******************  Bit definition for FSMC_BTR and FSMC_BWTR registers  ******************/\r
+#define  ACCMOD                28        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  DATLAT                        24       /*!<DATLA[3:0] bits (Data latency) */\r
+#define  CLKDIV                        20        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  BUSTURN               16        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  DATAST                8        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  ADDHLD                4        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  ADDSET                0       /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Analog to Digital Converter                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for ADC_SR register  ********************/\r
+#define  AWD                           0               /*!<Analog watchdog flag */\r
+#define  EOC                      1               /*!<End of conversion */\r
+#define  JEOC                     2               /*!<Injected channel end of conversion */\r
+#define  JSTRT                   3               /*!<Injected channel Start flag */\r
+#define  STRT                     4               /*!<Regular channel Start flag */\r
+\r
+/*******************  Bit definition for ADC_CR1 register  ********************/\r
+#define  AWDCH                  0            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define  EOCIE                         5           /*!<Interrupt enable for EOC */\r
+#define  AWDIE                         6              /*!<AAnalog Watchdog interrupt enable */\r
+#define  JEOCIE                  7           /*!<Interrupt enable for injected channels */\r
+#define  SCAN                    8           /*!<Scan mode */\r
+#define  AWDSGL               9             /*!<Enable the watchdog on a single channel in scan mode */\r
+#define  JAUTO                   10            /*!<Automatic injected group conversion */\r
+#define  DISCEN                  11            /*!<Discontinuous mode on regular channels */\r
+#define  JDISCEN                12             /*!<Discontinuous mode on injected channels */\r
+#define  DISCNUM               13           /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define  DUALMOD              16              /*!<DUALMOD[3:0] bits (Dual mode selection) */\r
+#define  JAWDEN                22             /*!<Analog watchdog enable on injected channels */\r
+#define  AWDEN                  23            /*!<Analog watchdog enable on regular channels */\r
+\r
+  \r
+/*******************  Bit definition for ADC_CR2 register  ********************/\r
+#define  ADON           0        //     ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */\r
+#define  CONT            1        //    ((uint32_t)0x00000002)        /*!<Continuous Conversion */\r
+#define  CAL               2     //     ((uint32_t)0x00000004)        /*!<A/D Calibration */\r
+#define  RSTCAL        3       //       ((uint32_t)0x00000008)        /*!<Reset Calibration */\r
+#define  DMA              8     //      ((uint32_t)0x00000100)        /*!<Direct Memory access mode */\r
+#define  ALIGN           11    //        ((uint32_t)0x00000800)        /*!<Data Alignment */\r
+#define  JEXTSEL        12     //             ((uint32_t)0x00007000)        /*!<JEXTSEL[2:0] bits (External event select for injected group) */\r
+#define  JEXTTRIG      15      //              ((uint32_t)0x00008000)        /*!<External Trigger Conversion mode for injected channels */\r
+#define  EXTSEL         17     //        ((uint32_t)0x000E0000)        /*!<EXTSEL[2:0] bits (External Event Select for regular group) */\r
+#define  EXTTRIG       20      //              ((uint32_t)0x00100000)        /*!<External Trigger Conversion mode for regular channels */\r
+#define  JSWSTART     21       //               ((uint32_t)0x00200000)        /*!<Start Conversion of injected channels */\r
+#define  SWSTART      22       //               ((uint32_t)0x00400000)        /*!<Start Conversion of regular channels */\r
+#define  TSVREFE       23      //              ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************  Bit definition for ADC_SMPR1 register  *******************/\r
+#define  SMP10            0    //        ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define  SMP11            3    //       ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define  SMP12            6    //        ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define  SMP13            9    //         ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define  SMP14            12   //         ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define  SMP15            15   //       ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define  SMP16            18   //        ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define  SMP17            21   //        ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+\r
+/******************  Bit definition for ADC_SMPR2 register  *******************/\r
+#define  SMP0             0    //        ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define  SMP1             3    //      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define  SMP2             6    //       ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define  SMP3             9    //       ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define  SMP4             12   //       ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define  SMP5             15           //       ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define  SMP6             18           //       ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define  SMP7             21   //        ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define  SMP8             24   //        ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define  SMP9             27   //       ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+\r
+/******************  Bit definition for ADC_JOFR1 register  *******************/\r
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */\r
+\r
+/******************  Bit definition for ADC_JOFR2 register  *******************/\r
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */\r
+\r
+/******************  Bit definition for ADC_JOFR3 register  *******************/\r
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */\r
+\r
+/******************  Bit definition for ADC_JOFR4 register  *******************/\r
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */\r
+\r
+/*******************  Bit definition for ADC_HTR register  ********************/\r
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */\r
+\r
+/*******************  Bit definition for ADC_LTR register  ********************/\r
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */\r
+\r
+/*******************  Bit definition for ADC_SQR1 register  *******************/\r
+#define  SQ13        0         //           ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define  SQ14        5         //          ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define  SQ15        10        //           ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define  SQ16        15        //             ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define  L               20            //        ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */\r
+\r
+/*******************  Bit definition for ADC_SQR2 register  *******************/\r
+#define  SQ7         0         //           ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define  SQ8         5         //          ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define  SQ9         10        //            ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define  SQ10       15         //            ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define  SQ11       20         //            ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define  SQ12       25         //            ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+\r
+/*******************  Bit definition for ADC_SQR3 register  *******************/\r
+#define  SQ1        0          //          ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define  SQ2        5          //          ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define  SQ3        10         //            ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define  SQ4        15         //            ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define  SQ5        20         //            ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define  SQ6        25         //           ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+\r
+/*******************  Bit definition for ADC_JSQR register  *******************/\r
+#define  JSQ1      0           //          ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  \r
+#define  JSQ2      5           //            ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define  JSQ3      10          //            ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define  JSQ4      15          //            ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define  JL           20               //        ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */\r
+\r
+/*******************  Bit definition for ADC_JDR1 register  *******************/\r
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR2 register  *******************/\r
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR3 register  *******************/\r
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR4 register  *******************/\r
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/********************  Bit definition for ADC_DR register  ********************/\r
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */\r
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */\r
+\r
+/*******************  Bit definition for DMA_IFCR register  *******************/\r
+#define  CGIF1              0          //       /*!< Channel 1 Global interrupt clearr */\r
+#define  CTCIF1            1           //       /*!< Channel 1 Transfer Complete clear */\r
+#define  CHTIF1            2           //        /*!< Channel 1 Half Transfer clear */\r
+#define  CTEIF1            3           //       /*!< Channel 1 Transfer Error clear */\r
+#define  CGIF2              4          //        /*!< Channel 2 Global interrupt clear */\r
+#define  CTCIF2            5           //        /*!< Channel 2 Transfer Complete clear */\r
+#define  CHTIF2            6           //        /*!< Channel 2 Half Transfer clear */\r
+#define  CTEIF2            7           //       /*!< Channel 2 Transfer Error clear */\r
+#define  CGIF3             8           //        /*!< Channel 3 Global interrupt clear */\r
+#define  CTCIF3            9          //        /*!< Channel 3 Transfer Complete clear */\r
+#define  CHTIF3            10        //        /*!< Channel 3 Half Transfer clear */\r
+#define  CTEIF3            11        //        /*!< Channel 3 Transfer Error clear */\r
+#define  CGIF4              12       //        /*!< Channel 4 Global interrupt clear */\r
+#define  CTCIF4            13       //       /*!< Channel 4 Transfer Complete clear */\r
+#define  CHTIF4            14       //       /*!< Channel 4 Half Transfer clear */\r
+#define  CTEIF4            15       //        /*!< Channel 4 Transfer Error clear */\r
+#define  CGIF5              16       //       /*!< Channel 5 Global interrupt clear */\r
+#define  CTCIF5            17       //        /*!< Channel 5 Transfer Complete clear */\r
+#define  CHTIF5            18       //        /*!< Channel 5 Half Transfer clear */\r
+#define  CTEIF5             19      //        /*!< Channel 5 Transfer Error clear */\r
+#define  CGIF6              20       //        /*!< Channel 6 Global interrupt clear */\r
+#define  CTCIF6            21       //        /*!< Channel 6 Transfer Complete clear */\r
+#define  CHTIF6            22       //        /*!< Channel 6 Half Transfer clear */\r
+#define  CTEIF6            23       //       /*!< Channel 6 Transfer Error clear */\r
+#define  CGIF7              24       //        /*!< Channel 7 Global interrupt clear */\r
+#define  CTCIF7            25       //        /*!< Channel 7 Transfer Complete clear */\r
+#define  CHTIF7            26       //        /*!< Channel 7 Half Transfer clear */\r
+#define  CTEIF7             27      //        /*!< Channel 7 Transfer Error clear */\r
+\r
+/*******************  Bit definition for DMA_CCRx register  *******************/\r
+#define  EN                    0               //         /*!< Channel enable*/\r
+#define  TCIE                  1               //            /*!< Transfer complete interrupt enable */\r
+#define  HTIE                  2               //           /*!< Half Transfer interrupt enable */\r
+#define  TEIE                  3               //            /*!< Transfer error interrupt enable */\r
+#define  DIR                   4               //           /*!< Data transfer direction */\r
+                                                       //                              0: Read from peripheral\r
+                                                       //                              1: Read from memory\r
+#define  CIRC                  5               //            /*!< Circular mode */\r
+                                                       //                              0: Circular mode disabled\r
+                                                       //                              1: Circular mode enabled\r
+#define  PINC                  6               //           /*!< Peripheral increment mode */\r
+                                                       //                              0: Peripheral increment mode disabled\r
+                                                       //                              1: Peripheral increment mode enabled\r
+#define  MINC                  7               //          /*!< Memory increment mode */\r
+                                                       //                              0: Memory increment mode disabled\r
+                                                       //                              1: Memory increment mode enabled\r
+#define  PSIZE                 8               //           /*!< PSIZE[1:0] bits (Peripheral size) */\r
+                                                       //                              00: 8-bits\r
+                                                       //                              01: 16-bits\r
+                                                       //                              10: 32-bits\r
+                                                       //                              11: Reserved\r
+#define  MSIZE         10          //           /*!< MSIZE[1:0] bits (Memory size) */\r
+                                                       //                              00: 8-bits\r
+                                                       //                              01: 16-bits\r
+                                                       //                              10: 32-bits\r
+                                                       //                              11: Reserved\r
+#define  PL                    12          //           /*!< PL[1:0] bits(Channel Priority level) */\r
+                                                       //                              00: Low\r
+                                                       //                              01: Medium\r
+                                                       //                              10: High\r
+                                                       //                              11: Very high\r
+#define  MEM2MEM       14          //           /*!< Memory to memory mode */\r
+\r
+\r
+extern U16             GTimer;\r
+extern U8              GTimeout;\r
+\r
+extern U16             TimerKeyScan;\r
+extern U8              GeneralBuf[];\r
+\r
+// ====================================================\r
+//     Macros\r
+//\r
+\r
+// ====================================================\r
+//     Function Prototype Declarations\r
+//\r
+void   Clock_Init(void);\r
+void Port_Init(void);\r
+void   USART1_Init(void);\r
+void   UartPutc(U8 ch, USART_TypeDef* USARTx);\r
+void   uputs(U8 *s, USART_TypeDef* USARTx);\r
+void   ADC2_Init(void);\r
+U16    ADC_Poll(ADC_TypeDef * adc, U8 chn);\r
+void   TIM3_Init(void);\r
+void   TIM4_Init(void);\r
+void   SysTick_Init(void);\r
+void   TFT_Init_Ili9341(void);\r
+void   write_comm(U8 commport);\r
+void write_data(U8 data);\r
+void assert_failed(U8 * file, U32 line);\r
+void NVIC_Configuration(void);\r
+void   OutputTLvl(void);\r
+\r
+#endif // Board_h\r
+\r
+\r
diff --git a/Command.c b/Command.c
new file mode 100644 (file)
index 0000000..9363a81
--- /dev/null
+++ b/Command.c
@@ -0,0 +1,640 @@
+//////////////////////////////////////////////////////////////////////////////\r
+//\r
+//     Filename:       Command.c\r
+//     Version:                \r
+//     Data:           \r
+//\r
+//     Author:         Liu, Zemin\r
+//     Company:        JYE Tech\r
+//\r
+//-----------------------------------------------------------------------------\r
+//\r
+//     Target:                 STM32F103C8 \r
+//     Tool chain:     CodeSourcery G++\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Required files:\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Notes:\r
+//\r
+//\r
+//-----------------------------------------------------------------------------\r
+//     Revision History:\r
+//\r
+///////////////////////////////////////////////////////////////////////////////\r
+#include "stm32f10x.h"\r
+#include "stm32f10x_conf.h"\r
+\r
+#include "Common.h"\r
+#include "Board.h"\r
+#include "Command.h"\r
+#include       "libdso138.h"\r
+#include       "Screen.h"\r
+#include       "Eeprom.h"\r
+\r
+// ===========================================================
+//     File Scope Global variables
+// ===========================================================
+//\r
+const  KeyScanCode KScanCodeTab[9] = {\r
+//     scan code       key code                key param\r
+       {0x7FFF,        KC_SW1,         '1'},           // 1\r
+       {0xBFFF,        KC_SW2,         '2'},           // 2\r
+       {0xDFFF,        KC_SW3,         '3'},           // 3\r
+       {0xEFFF,        KC_SW4,         '4'},           // 4\r
+       {0x7FFE,        KC_SW1H,        '5'},           // 5\r
+       {0xBFFE,        KC_SW2H,        '6'},           // 6\r
+       {0xDFFE,        KC_SW3H,        '7'},           // 7\r
+       {0xEFFE,        KC_SW4H,        '8'},           // 8\r
+       {0,                     0,                      0}              \r
+       };\r
+\r
+KEYPAD Keypad;\r
+U8     VSenPrev, CplPrev;\r
+U16    Flags;\r
+\r
+\r
+// ===========================================================
+//     Function Definitions
+// ===========================================================
+//\r
+void   AppInit()
+{\r
+ U16 tmp0;\r
+\r
+// =============================\r
+// Note: DSO_Init() must be executed for proper capture engine running\r
\r
+ DSO_Init();\r
+\r
+// =============================\r
+\r
+ // Check EEPROM for valid settings\r
+ EE_ReadVariable(Addr_SettingStatus, &tmp0);\r
+ if(tmp0 == SettingStatus_Initialized) {\r
+       // Load saved settings\r
+       EE_ReadVariable(VirtAddVarTab[Addr_Vpos], &tmp0);\r
+       SetVPos(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_Vsen], &tmp0);\r
+       SetVSen(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_Cpl], &tmp0);\r
+       SetCpl(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_TimeBase], &tmp0);\r
+       SetTimeBase(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_TrigMode], &tmp0);\r
+       SetTrigMode(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_TrigEdge], &tmp0);\r
+       SetTrigEdge(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_TrigLvl], &tmp0);\r
+       SetTrigLvl(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_RecLen], &tmp0);\r
+       SetRecLen(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_HPos], &tmp0);\r
+       SetHPos(tmp0);\r
+       EE_ReadVariable(VirtAddVarTab[Addr_VPosOfs], &tmp0);\r
+       SetVPosOfs(tmp0);\r
+       }\r
+ else {\r
+       // Load default settings and initialize EEPROM\r
+       SetVPos(0);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_Vpos], 0);\r
+       SetVSen(VS_05V);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_Vsen], VS_05V);\r
+       SetCpl(CP_DC);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_Cpl], CP_DC);\r
+       SetTimeBase(TB_1ms);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_TimeBase], TB_1ms);\r
+       SetTrigMode(TM_Auto);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_TrigMode], TM_Auto);\r
+       SetTrigEdge(TE_Falling);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_TrigEdge], TE_Falling);\r
+       SetTrigLvl(0);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_TrigLvl], 0);\r
+       SetRecLen(SampleBufSizeMax);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_RecLen], SampleBufSizeMax);\r
+       SetHPos(GetRecLen()/2 - WDsize/2);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_HPos], GetRecLen()/2 - WDsize/2);\r
+       SetVPosOfs(0);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_VPosOfs], 0);\r
+\r
+       // Mark down EEPROM has been initialized\r
+       EE_WriteVariable(VirtAddVarTab[Addr_SettingStatus], SettingStatus_Initialized);\r
+\r
+       }\r
+\r
+ OutputTLvl();\r
+\r
+ // Misc initialization
+ TimerKeyScan = 1;\r
+
+ Keypad.KDebounceVal = KD_val;
+}\r
+\r
+void   KeyProc(void)\r
+{\r
+ switch(Keypad.KeyCode) {\r
+       case KC_SW1:\r
+               DoKeyOk();\r
+       default:        \r
+               break;\r
+               \r
+       case KC_SW2:\r
+               DoKeyInc();\r
+               break;\r
+\r
+       case KC_SW3:\r
+               DoKeyDec();\r
+               break;\r
+\r
+       case KC_SW4:\r
+               DoKeySel();\r
+               break;\r
+\r
+       case KC_SW1H:\r
+               DoKeyOkH();\r
+               break;\r
+\r
+       case KC_SW2H:\r
+               DoKeyIncH();\r
+               break;\r
+\r
+       case KC_SW3H:\r
+               DoKeyDecH();\r
+               break;\r
+\r
+       case KC_SW4H:\r
+               DoKeySelH();\r
+               break;\r
+\r
+       }\r
+}\r
+\r
+\r
+void KeyScan(void)
+{
+ U16   tmp1;\r
+ U8    tmp2, tmp3;\r
+
+ Keypad.KScanBuf = NoKey;\r
+ // Read buttons
+ tmp1 = (PB_Port & PB_Bits) | ~PB_Bits;
+ if(tmp1 != NoKey) {
+       Keypad.KScanBuf = tmp1;\r
+       }
+
+ // -- Debouncing
+ if((Keypad.KScanBuf == NoKey) || (Keypad.KScanBuf != Keypad.KScanCode)) {\r
+       Keypad.KScanCode = Keypad.KScanBuf;\r
+       Keypad.KCount = 0;\r
+       Keypad.KHCount = 0;\r
+       Keypad.KTimeChk = KH_val;\r
+       }
+ else {
+       Keypad.KCount++;\r
+       if(Keypad.KCount > Keypad.KDebounceVal) {\r
+               if(Keypad.KCount == Keypad.KDebounceVal + 3) {\r
+                       Keypad.KCount = Keypad.KDebounceVal;\r
+                       if(++Keypad.KHCount == Keypad.KTimeChk) {\r
+                               // Key hold detected
+                               Keypad.KScanCode &= 0xFFFE;\r
+                               KeyConvert((KeyScanCode *)KScanCodeTab, Keypad.KScanCode);\r
+                               // Change KTimeChk for key repeat
+                               Keypad.KTimeChk += KR_Time;\r
+                               }
+                       }
+               }
+       else if(Keypad.KCount == Keypad.KDebounceVal) {\r
+               // Key push detected
+               KeyConvert((KeyScanCode *)KScanCodeTab, Keypad.KScanCode);\r
+               }
+       }
+\r
+#define        Threshold_High          0x0900\r
+#define        Threshold_Low           0x0300\r
+\r
+ // Read switch SEN1\r
+ tmp1 = ADC_Poll(ADC2, 2);\r
+ tmp2 = 0;\r
+ if(tmp1 > Threshold_High) {\r
+       tmp2 = 2;\r
+       }\r
+ else if(tmp1 > Threshold_Low) {\r
+       tmp2 = 1;\r
+       }\r
+\r
+ // Read switch SEN2\r
+ tmp1 = ADC_Poll(ADC2, 1);\r
+ tmp3 = 0;\r
+ if(tmp1 > Threshold_High) {\r
+       tmp3 = 2;\r
+       }\r
+ else if(tmp1 > Threshold_Low) {\r
+       tmp3 = 1;\r
+       }\r
+\r
+ // Determine VSen setting\r
+ tmp2 = 3 * tmp2 + tmp3 + VSenMin;\r
+ if(tmp2 != VSenPrev) {\r
+       SetVSen(tmp2);\r
+       VSenPrev = tmp2;\r
+       UpdateDisp(Disp_Param);\r
+       }\r
\r
+ // Read switch Cpl\r
+ tmp1 = ADC_Poll(ADC2, 3);\r
+ tmp2 = 0;\r
+ if(tmp1 > Threshold_High) {\r
+       tmp2 = 2;\r
+       }\r
+ else if(tmp1 > Threshold_Low) {\r
+       tmp2 = 1;\r
+       }\r
+ tmp2 = 2 - tmp2;\r
\r
+ // Determine Cpl setting\r
+ if(tmp2 != CplPrev) {\r
+       SetCpl(tmp2);\r
+       CplPrev = tmp2;\r
+       UpdateDisp(Disp_Param);\r
+       }\r
+ }
+
+void   KeyConvert(KeyScanCode *KSCTab, U16 KSCode)
+{
+ U16 tmp1;
+ while((tmp1 = *(U16 *)(KSCTab + 0))) {
+       if(tmp1 == KSCode) {
+               // -- Match found
+               Keypad.KeyCode = *(U8 *)((U8 *)KSCTab + 2);\r
+               Keypad.KeyCodeBuf = Keypad.KeyCode;\r
+               Keypad.KeyParam = *(U8 *)((U8 *)KSCTab + 3);\r
+               return;
+               }
+       else {
+               // -- Proceed to next entry
+               KSCTab = (KeyScanCode *)((U8 *)KSCTab + sizeof(KeyScanCode));
+               }
+       
+       }
+}
+\r
+void   DoKeyOk(void)
+{\r
+ U16 tmp;\r
\r
+ tmp = GetDsoStatus();\r
+ // Toggle HOLD state
+ BitXor(tmp, DSO_Hold);\r
+\r
+ if(BitTest(tmp, DSO_Hold)) {\r
+       // Set HOLD \r
+       SetHold();\r
+       // Stop capture\r
+       StopCapture();\r
+       }\r
+ else {\r
+       // Clear HOLD\r
+       ClrHold();\r
+       // Start capture at exit of HOLD
+       StartCapture();
+       }\r
+ UpdateDisp(Disp_Param);\r
+}\r
+
+void   DoKeyInc(void)
+{
+ S8    tmp0;
+ S16   tmp1;
+ switch(GetFocus()) {\r
+       case FC_Timebase:
+               tmp0 = GetTimebase();\r
+               tmp0++;
+               tmp0 = SetTimeBase(tmp0);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TimeBase], tmp0);\r
+               if(tmp0 >= TB_20ms) {\r
+                       // Restart capture
+                       StartCapture();
+                       }\r
+               else {
+                       // Change sampling rate only
+                       UpdateTimebase();\r
+                       }
+               // Make key debounce time shorter for these TB's \r
+               if((tmp0 < TB_20ms) && (tmp0 > TB_1s)) {\r
+                       Keypad.KDebounceVal = KD_val1;
+                       }
+               else {
+                       Keypad.KDebounceVal = KD_val;
+                       }
+       default:        
+               break;
+               
+       case FC_TrigMode:
+               tmp0 = GetTrigMode();\r
+               tmp0++;
+               tmp0 = SetTrigMode(tmp0);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TrigMode], tmp0);\r
+               // Restart capture. \r
+               StartCapture();
+               break;\r
+
+       case FC_TrigEdge:
+               tmp0 = GetTrigEdge();\r
+               tmp0++;
+               tmp0 = SetTrigEdge(tmp0);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TrigEdge], tmp0);\r
+               break;
+               
+       case FC_VPos:
+               tmp1 = GetVPos();\r
+               tmp1++;
+               tmp1 = SetVPos(tmp1);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_Vpos], tmp1);\r
+               UpdateDisp(Disp_Trace);\r
+               break;
+
+       case FC_TrigLvl:
+               tmp1 = GetTrigLvl();\r
+               tmp1++;
+               tmp1 = SetTrigLvl(tmp1);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TrigLvl], tmp1);\r
+               OutputTLvl();\r
+               break;
+               
+       case FC_HPos:
+               // Move waveform right
+               tmp1 = GetHPos();\r
+               tmp1--;
+               tmp1 = SetHPos(tmp1);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_HPos], tmp1);\r
+               UpdateDisp(Disp_Trace);\r
+               break;
+               
+       }
+ UpdateDisp(Disp_Param);\r
+}
+
+void   DoKeyDec(void)
+{
+ S8    tmp0;
+ S16   tmp1;
+ switch(GetFocus()) {\r
+       case FC_Timebase:
+               tmp0 = GetTimebase();\r
+               tmp0--;
+               tmp0 = SetTimeBase(tmp0);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TimeBase], tmp0);\r
+               if(tmp0 >= TB_50ms) {\r
+                       // Restart capture
+//                     UartPutc('7', USART1);\r
+                       StartCapture();
+//                     UartPutc('1', USART1);\r
+                       }\r
+               else {
+                       // Change sampling rate only
+                       UpdateTimebase();\r
+                       \r
+                       }
+/*             \r
+               // Make key debounce time shorter for these TB's \r
+               if((tmp0 < TB_20ms) && (tmp0 > TB_1s)) {\r
+                       Delay(50000);   // To avoid same keypress repeated\r
+                       Keypad.KDebounceVal = KD_val1;
+                       }
+               else {
+                       Keypad.KDebounceVal = KD_val;
+                       }\r
+*/             \r
+       default:        
+               break;
+               
+       case FC_TrigMode:
+               tmp0 = GetTrigMode();\r
+               tmp0--;
+               tmp0 = SetTrigMode(tmp0);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TrigMode], tmp0);\r
+               // Restart capture. \r
+               StartCapture();
+               break;\r
+
+       case FC_TrigEdge:
+               tmp0 = GetTrigEdge();\r
+               tmp0--;
+               tmp0 = SetTrigEdge(tmp0);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TrigEdge], tmp0);\r
+               break;
+               
+       case FC_VPos:
+               tmp1 = GetVPos();\r
+               tmp1--;
+               tmp1 = SetVPos(tmp1);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_Vpos], tmp1);\r
+               UpdateDisp(Disp_Trace);\r
+               break;
+
+       case FC_TrigLvl:
+               tmp1 = GetTrigLvl();\r
+               tmp1--;
+               tmp1 = SetTrigLvl(tmp1);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_TrigLvl], tmp1);\r
+               OutputTLvl();\r
+               break;
+               
+       case FC_HPos:
+               // Move waveform left
+               tmp1 = GetHPos();\r
+               tmp1++;
+               tmp1 = SetHPos(tmp1);\r
+               EE_WriteVariable(VirtAddVarTab[Addr_HPos], tmp1);\r
+               UpdateDisp(Disp_Trace);\r
+               break;
+               
+       }
+ UpdateDisp(Disp_Param);\r
+}
+
+void   DoKeySel(void)
+{\r
+ U8 tmp;\r
+\r
+ tmp = GetFocus();\r
+ tmp++;\r
+ if(tmp >= FC_Max) {\r
+       tmp = 0;\r
+       }\r
+ SetFocus(tmp);\r
+\r
+ UpdateDisp(Disp_Param);\r
+}\r
+
+void   DoKeyOkH(void)
+{\r
+ S16 tmp1;\r
\r
+ if(GetFocus() == FC_VPos) {\r
+       // Do VPos alignment\r
+       tmp1 = (S16)(GetAverage() - WWindowMidValue);\r
+       SetVPosOfs(tmp1);\r
+       EE_WriteVariable(VirtAddVarTab[Addr_VPosOfs], tmp1);\r
+       }\r
+}
+
+void   DoKeyIncH(void)
+{
+ S16   tmp1;
+ switch(GetFocus()) {\r
+       case FC_VPos:
+               tmp1 = GetVPos();\r
+               tmp1 += 10;
+               SetVPos(tmp1);
+               break;
+
+       case FC_TrigLvl:
+               tmp1 = GetTrigLvl();\r
+               tmp1 += 10;
+               SetTrigLvl(tmp1);
+               OutputTLvl();\r
+               break;
+               
+       case FC_HPos:
+               // Move waveform right
+               tmp1 = GetHPos();\r
+               tmp1 -= 20;
+               SetHPos(tmp1);          
+               break;
+       }
+
+ UpdateDisp(Disp_Param);\r
+}
+
+void   DoKeyDecH(void)
+{
+ S16   tmp1;
+ switch(GetFocus()) {\r
+       case FC_VPos:
+               tmp1 = GetVPos();\r
+               tmp1 -= 10;
+               SetVPos(tmp1);
+               break;
+
+       case FC_TrigLvl:
+               tmp1 = GetTrigLvl();\r
+               tmp1 -= 10;
+               SetTrigLvl(tmp1);
+               OutputTLvl();\r
+               break;
+               
+       case FC_HPos:
+               // Move waveform left
+               tmp1 = GetHPos();\r
+               tmp1 += 20;
+               SetHPos(tmp1);
+               break;
+       }
+
+ UpdateDisp(Disp_Param);\r
+}
+
+void   DoKeySelH(void)
+{\r
+\r
+}\r
+\r
+void   LedBlink(void)\r
+{\r
+ U16   tmp;\r
\r
+ // Turn on LED\r
+ Port_BitClr(LED_Base, (1 << LED_Bit));\r
+ tmp = 20;\r
+ while(tmp) {\r
+       Delay(65000);\r
+       tmp--;\r
+       }\r
\r
+ // Turn off LED\r
+ Port_BitSet(LED_Base, (1 << LED_Bit));\r
+ tmp = 20;\r
+ while(tmp) {\r
+       Delay(65000);\r
+       tmp--;\r
+       }\r
+\r
+ // Turn on LED\r
+ Port_BitClr(LED_Base, (1 << LED_Bit));\r
+ tmp = 20;\r
+ while(tmp) {\r
+       Delay(65000);\r
+       tmp--;\r
+       }\r
\r
+ // Turn off LED\r
+ Port_BitSet(LED_Base, (1 << LED_Bit));\r
+}\r
+\r
+void   TestMode(void)\r
+{\r
+ U16 tmp;\r
\r
+ // Change system clock to HSI\r
+ RCC->CFGR &= ~RCC_CFGR_SW;\r
+ RCC->CFGR |= RCC_CFGR_SW_HSI;\r
+\r
+ // Disable JTAG and SWD\r
+ AFIO->MAPR &= ~AFIO_MAPR_SWJ_CFG;\r
+ AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_2;\r
+\r
+ // Remap PD0 & PD1 to make them available as GPIO\r
+ AFIO->MAPR |= AFIO_MAPR_PD01_REMAP;\r
+\r
+ // Set all ports to output mode\r
+ GPIOA->CRL = 0x33333333;\r
+ GPIOA->CRH = 0x33333333;\r
+\r
+ GPIOB->CRL = 0x33333333;\r
+ GPIOB->CRH = 0x33333333;\r
+\r
+ GPIOC->CRL = 0x33333333;\r
+ GPIOC->CRH = 0x33333333;\r
\r
+ GPIOD->CRL = 0x33333333;\r
+ GPIOD->CRH = 0x33333333;\r
+\r
+ // Blink LEDs\r
+ while(1) {\r
+       GPIOA->ODR = 0x5555;\r
+       GPIOB->ODR = 0x5555;\r
+       GPIOC->ODR = 0x5555;\r
+       GPIOD->ODR = 0x5555;\r
+\r
+       tmp = 5;\r
+       while(tmp) {\r
+               Delay(60000);\r
+               tmp--;\r
+               }\r
+\r
+       GPIOA->ODR = 0xAAAA;\r
+       GPIOB->ODR = 0xAAAA;\r
+       GPIOC->ODR = 0xAAAA;\r
+       GPIOD->ODR = 0xAAAA;\r
+\r
+       tmp = 5;\r
+       while(tmp) {\r
+               Delay(60000);\r
+               tmp--;\r
+               }\r
+       }\r
\r
+}\r
+\r
diff --git a/Command.h b/Command.h
new file mode 100644 (file)
index 0000000..5301749
--- /dev/null
+++ b/Command.h
@@ -0,0 +1,129 @@
+//////////////////////////////////////////////////////////////////////////////
+//
+//     Filename:       Command.h
+//     Version:                
+//     Data:           
+//
+//     Author:         Liu, Zemin
+//     Company:        JYE Tech
+//
+//-----------------------------------------------------------------------------
+//
+//     Target:                 STM32F103C8 
+//     Tool chain:     CodeSourcery G++
+//
+//-----------------------------------------------------------------------------
+//     Required files:
+//
+//-----------------------------------------------------------------------------
+//     Notes:
+//
+//
+//-----------------------------------------------------------------------------
+//     Revision History:
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+#ifndef        Command_h
+#define        Command_h
+
+#include       "Common.h"
+
+// ============== Key Analysis Definitions =====================
+
+typedef        struct {
+       // Keypad processing variables
+       U16     Flags;
+       U16     KScanBuf;
+       U16     KScanCode;
+       U16     KeyCode;
+       U16     KeyParam;
+       U16     KeyCodeBuf;
+       U16     KCount;                 // Key debounce counter
+       U16     KDebounceVal;   // Debounce timing length (number of scans)
+       U16     KHCount;                // Key hold counter
+       U16     KTimeChk;               // Key time check 
+
+       } KEYPAD;
+
+enum   KeypadFlags {
+       KF_DoKeyScan            = 0,
+
+       };
+
+// -- Key-Event mapping 
+typedef        struct  {
+       U8      Keycode;
+       U8      Event;
+       }KeyEvent ;
+
+// -- Key code conversion 
+typedef        struct  {
+       U16     ScanCode;
+       U8      Keycode;
+       }KeyMap ;
+
+// --------------------------------------
+// Keypad 
+typedef        struct  {
+       U16     ScanCode;
+       U8      KeyCode;
+       U8      KeyParam;
+       }KeyScanCode;
+
+// -- Key Code Definitions 
+enum   KeyCodes {
+       KC_void = 0,                            
+       KC_SW1,                         
+       KC_SW2,                         
+       KC_SW3,                         
+       KC_SW4,                         
+       KC_SW1H,                                
+       KC_SW2H,                                
+       KC_SW3H,                                
+       KC_SW4H,                
+       };
+
+// Pushbutton processing parameters
+#define        NoKey                   0xFFFF  
+
+#define        KD_val                  2               // 
+#define        KD_val1                 5               // 
+#define        KH_val                  20              // 
+#define        KR_Time         1       
+
+// Setting status
+#define        SettingStatus_Initialized               0xF3C5
+
+
+// ===========================================================
+//     Export variables
+// ===========================================================
+//
+extern KEYPAD  Keypad;
+extern U16     Flags;
+
+// ===========================================================
+//     Function Declarations
+// ===========================================================
+//
+void   AppInit();
+void KeyScan(void);
+void   KeyConvert(KeyScanCode *KSCTab, U16 KSCode);
+U8     KeyEventMap(U8 keycode, KeyEvent *kvmap);
+void   KeyProc(void);
+void   DoKeyOk(void);
+void   DoKeyInc(void);
+void   DoKeyDec(void);
+void   DoKeySel(void);
+void   DoKeyOkH(void);
+void   DoKeyIncH(void);
+void   DoKeyDecH(void);
+void   DoKeySelH(void);
+void   LedBlink(void);
+void   TestMode(void);
+
+
+#endif
+
diff --git a/Common.c b/Common.c
new file mode 100644 (file)
index 0000000..3c14262
--- /dev/null
+++ b/Common.c
@@ -0,0 +1,41 @@
+//////////////////////////////////////////////////////////////////////////////
+//
+//     Filename:       Common.c
+//     Version:                
+//     Data:           
+//
+//     Author:         Liu, Zemin
+//     Company:        JYE Tech
+//
+//-----------------------------------------------------------------------------
+//
+//     Target:                 STM32F103C8 
+//     Tool chain:     CodeSourcery G++
+//
+//
+//-----------------------------------------------------------------------------
+//     Required files:
+//
+//-----------------------------------------------------------------------------
+//     Notes:
+//
+//
+//-----------------------------------------------------------------------------
+//     Revision History:
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+//-----------------------------------------------------------------------------
+//     Includes
+//-----------------------------------------------------------------------------
+
+#include       "Common.h"
+
+void   Delay(volatile U16 count)
+{
+ while(count) {
+       count--;
+       }
+}
+
+
diff --git a/Common.h b/Common.h
new file mode 100644 (file)
index 0000000..78ed5c4
--- /dev/null
+++ b/Common.h
@@ -0,0 +1,70 @@
+//////////////////////////////////////////////////////////////////////////////
+//
+//     Filename:       Common.h
+//     Version:                
+//     Data:           
+//
+//     Author:         Liu, Zemin
+//     Company:        JYE Tech
+//
+//-----------------------------------------------------------------------------
+//
+//     Target:                 STM32F103C8 
+//     Tool chain:     CodeSourcery G++
+//
+//
+//-----------------------------------------------------------------------------
+//     Required files:
+//
+//-----------------------------------------------------------------------------
+//     Notes:
+//
+//
+//-----------------------------------------------------------------------------
+//     Revision History:
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+
+#ifndef Common_h
+
+#define        Common_h
+
+typedef        unsigned char           U8;
+typedef        signed char             S8;
+typedef        unsigned short int      U16;
+typedef        signed short int        S16;
+typedef        unsigned long           U32;
+typedef        signed long             S32;
+
+typedef        void    (*FuncPointer)(U8); 
+typedef        void    (*CmdFuncPointer)(void); 
+typedef        void    (*StateAction)(void); 
+
+// -- Control debug code generation
+//#define      _Debug_
+
+// ============= Macro definitions ===========================
+
+#define        BitSet(word, bit_mask)          ((word) |= (bit_mask))
+#define        BitClr(word, bit_mask)          ((word) &= ~(bit_mask))
+#define        BitTest(word, bit_mask)         ((word) & (bit_mask))
+#define        BitAnd(word, bit_mask)          ((word) &= (bit_mask))
+#define        BitOr(word, bit_mask)           ((word) |= (bit_mask))
+#define        BitXor(word, bit_mask)          ((word) ^= (bit_mask))
+
+#define        Port_BitSet(port, bit_mask)     (port->BSRR = bit_mask)
+#define        Port_BitClr(port, bit_mask)     (port->BRR = bit_mask)
+
+#define        SetToLow(port, bit_mask)                (port->BRR = bit_mask)          
+#define        SetToHigh(port, bit_mask)       (port->BSRR = bit_mask)         
+
+
+// ===========================================================
+//     Function Prototype Declarations
+// ===========================================================
+//
+void   Delay(U16 count);
+
+#endif // Common_h 
+
diff --git a/Eeprom.c b/Eeprom.c
new file mode 100644 (file)
index 0000000..af87bb0
--- /dev/null
+++ b/Eeprom.c
@@ -0,0 +1,630 @@
+/**\r
+  ******************************************************************************\r
+  * @file    EEPROM_Emulation/src/eeprom.c \r
+  * @author  MCD Application Team\r
+  * @version V3.1.0\r
+  * @date    07/27/2009\r
+  * @brief   This file provides all the EEPROM emulation firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+  */ \r
+/** @addtogroup EEPROM_Emulation\r
+  * @{\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "eeprom.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+FLASH_Status FlashStatus;\r
+\r
+\r
+// Virtual address defined by the user: 0xFFFF value is prohibited \r
+uint16_t VirtAddVarTab[NumbOfVar] = {\r
+       Addr_TimeBase,\r
+       Addr_HPos,\r
+       Addr_Vsen,\r
+       Addr_Cpl,\r
+       Addr_Vpos,\r
+       Addr_VPosOfs,\r
+       Addr_TrigMode,\r
+       Addr_TrigEdge,\r
+       Addr_TrigLvl,\r
+       Addr_TrigPos,\r
+       Addr_RecLen,\r
+       Addr_SettingStatus,\r
+       \r
+       };\r
+\r
+/* Global variable used to store variable value in read sequence */\r
+uint16_t DataVar = 0;\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+static FLASH_Status EE_Format(void);\r
+static uint16_t EE_FindValidPage(uint8_t Operation);\r
+static uint16_t EE_VerifyPageFullWriteVariable(uint16_t VirtAddress, uint16_t Data);\r
+static uint16_t EE_PageTransfer(uint16_t VirtAddress, uint16_t Data);\r
+\r
+/**\r
+  * @brief  Restore the pages to a known good state in case of page's status\r
+  *   corruption after a power loss.\r
+  * @param  None.\r
+  * @retval - Flash error code: on write Flash error\r
+  *         - FLASH_COMPLETE: on success\r
+  */\r
+uint16_t EE_Init(void)\r
+{\r
+  uint16_t PageStatus0 = 6, PageStatus1 = 6;\r
+  uint16_t VarIdx = 0;\r
+  uint16_t EepromStatus = 0, ReadStatus = 0;\r
+  int16_t x = -1;\r
+  uint16_t  FlashStatus;\r
+\r
+  /* Get Page0 status */\r
+  PageStatus0 = (*(__IO uint16_t*)PAGE0_BASE_ADDRESS);\r
+  /* Get Page1 status */\r
+  PageStatus1 = (*(__IO uint16_t*)PAGE1_BASE_ADDRESS);\r
+\r
+  /* Check for invalid header states and repair if necessary */\r
+  switch (PageStatus0)\r
+  {\r
+    case ERASED:\r
+      if (PageStatus1 == VALID_PAGE) /* Page0 erased, Page1 valid */\r
+      {\r
+        /* Erase Page0 */\r
+        FlashStatus = FLASH_ErasePage(PAGE0_BASE_ADDRESS);\r
+        /* If erase operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      else if (PageStatus1 == RECEIVE_DATA) /* Page0 erased, Page1 receive */\r
+      {\r
+        /* Erase Page0 */\r
+        FlashStatus = FLASH_ErasePage(PAGE0_BASE_ADDRESS);\r
+        /* If erase operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+        /* Mark Page1 as valid */\r
+        FlashStatus = FLASH_ProgramHalfWord(PAGE1_BASE_ADDRESS, VALID_PAGE);\r
+        /* If program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      else /* First EEPROM access (Page0&1 are erased) or invalid state -> format EEPROM */\r
+      {\r
+        /* Erase both Page0 and Page1 and set Page0 as valid page */\r
+        FlashStatus = EE_Format();\r
+        /* If erase/program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      break;\r
+\r
+    case RECEIVE_DATA:\r
+      if (PageStatus1 == VALID_PAGE) /* Page0 receive, Page1 valid */\r
+      {\r
+        /* Transfer data from Page1 to Page0 */\r
+        for (VarIdx = 0; VarIdx < NumbOfVar; VarIdx++)\r
+        {\r
+          if (( *(__IO uint16_t*)(PAGE0_BASE_ADDRESS + 6)) == VirtAddVarTab[VarIdx])\r
+          {\r
+            x = VarIdx;\r
+          }\r
+          if (VarIdx != x)\r
+          {\r
+            /* Read the last variables' updates */\r
+            ReadStatus = EE_ReadVariable(VirtAddVarTab[VarIdx], &DataVar);\r
+            /* In case variable corresponding to the virtual address was found */\r
+            if (ReadStatus != 0x1)\r
+            {\r
+              /* Transfer the variable to the Page0 */\r
+              EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddVarTab[VarIdx], DataVar);\r
+              /* If program operation was failed, a Flash error code is returned */\r
+              if (EepromStatus != FLASH_COMPLETE)\r
+              {\r
+                return EepromStatus;\r
+              }\r
+            }\r
+          }\r
+        }\r
+        /* Mark Page0 as valid */\r
+        FlashStatus = FLASH_ProgramHalfWord(PAGE0_BASE_ADDRESS, VALID_PAGE);\r
+        /* If program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+        /* Erase Page1 */\r
+        FlashStatus = FLASH_ErasePage(PAGE1_BASE_ADDRESS);\r
+        /* If erase operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      else if (PageStatus1 == ERASED) /* Page0 receive, Page1 erased */\r
+      {\r
+        /* Erase Page1 */\r
+        FlashStatus = FLASH_ErasePage(PAGE1_BASE_ADDRESS);\r
+        /* If erase operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+        /* Mark Page0 as valid */\r
+        FlashStatus = FLASH_ProgramHalfWord(PAGE0_BASE_ADDRESS, VALID_PAGE);\r
+        /* If program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      else /* Invalid state -> format eeprom */\r
+      {\r
+        /* Erase both Page0 and Page1 and set Page0 as valid page */\r
+        FlashStatus = EE_Format();\r
+        /* If erase/program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      break;\r
+\r
+    case VALID_PAGE:\r
+      if (PageStatus1 == VALID_PAGE) /* Invalid state -> format eeprom */\r
+      {\r
+        /* Erase both Page0 and Page1 and set Page0 as valid page */\r
+        FlashStatus = EE_Format();\r
+        /* If erase/program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      else if (PageStatus1 == ERASED) /* Page0 valid, Page1 erased */\r
+      {\r
+        /* Erase Page1 */\r
+        FlashStatus = FLASH_ErasePage(PAGE1_BASE_ADDRESS);\r
+        /* If erase operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      else /* Page0 valid, Page1 receive */\r
+      {\r
+        /* Transfer data from Page0 to Page1 */\r
+        for (VarIdx = 0; VarIdx < NumbOfVar; VarIdx++)\r
+        {\r
+          if ((*(__IO uint16_t*)(PAGE1_BASE_ADDRESS + 6)) == VirtAddVarTab[VarIdx])\r
+          {\r
+            x = VarIdx;\r
+          }\r
+          if (VarIdx != x)\r
+          {\r
+            /* Read the last variables' updates */\r
+            ReadStatus = EE_ReadVariable(VirtAddVarTab[VarIdx], &DataVar);\r
+            /* In case variable corresponding to the virtual address was found */\r
+            if (ReadStatus != 0x1)\r
+            {\r
+              /* Transfer the variable to the Page1 */\r
+              EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddVarTab[VarIdx], DataVar);\r
+              /* If program operation was failed, a Flash error code is returned */\r
+              if (EepromStatus != FLASH_COMPLETE)\r
+              {\r
+                return EepromStatus;\r
+              }\r
+            }\r
+          }\r
+        }\r
+        /* Mark Page1 as valid */\r
+        FlashStatus = FLASH_ProgramHalfWord(PAGE1_BASE_ADDRESS, VALID_PAGE);\r
+        /* If program operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+        /* Erase Page0 */\r
+        FlashStatus = FLASH_ErasePage(PAGE0_BASE_ADDRESS);\r
+        /* If erase operation was failed, a Flash error code is returned */\r
+        if (FlashStatus != FLASH_COMPLETE)\r
+        {\r
+          return FlashStatus;\r
+        }\r
+      }\r
+      break;\r
+\r
+    default:  /* Any other state -> format eeprom */\r
+      /* Erase both Page0 and Page1 and set Page0 as valid page */\r
+      FlashStatus = EE_Format();\r
+      /* If erase/program operation was failed, a Flash error code is returned */\r
+      if (FlashStatus != FLASH_COMPLETE)\r
+      {\r
+        return FlashStatus;\r
+      }\r
+      break;\r
+  }\r
+\r
+  return FLASH_COMPLETE;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the last stored variable data, if found, which correspond to\r
+  *   the passed virtual address\r
+  * @param  VirtAddress: Variable virtual address\r
+  * @param  Data: Global variable contains the read variable value\r
+  * @retval Success or error status:\r
+  *           - 0: if variable was found\r
+  *           - 1: if the variable was not found\r
+  *           - NO_VALID_PAGE: if no valid page was found.\r
+  */\r
+uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t* Data)\r
+{\r
+  uint16_t ValidPage = PAGE0;\r
+  uint16_t AddressValue = 0x5555, ReadStatus = 1;\r
+  uint32_t Address = 0x08010000, PageStartAddress = 0x08010000;\r
+\r
+  /* Get active Page for read operation */\r
+  ValidPage = EE_FindValidPage(READ_FROM_VALID_PAGE);\r
+\r
+  /* Check if there is no valid page */\r
+  if (ValidPage == NO_VALID_PAGE)\r
+  {\r
+    return  NO_VALID_PAGE;\r
+  }\r
+\r
+  /* Get the valid Page start Address */\r
+  PageStartAddress = (uint32_t)(EEPROM_START_ADDRESS + (uint32_t)(ValidPage * PAGE_SIZE));\r
+\r
+  /* Get the valid Page end Address */\r
+  Address = (uint32_t)((EEPROM_START_ADDRESS - 2) + (uint32_t)((1 + ValidPage) * PAGE_SIZE));\r
+\r
+  /* Check each active page address starting from end */\r
+  while (Address > (PageStartAddress + 2))\r
+  {\r
+    /* Get the current location content to be compared with virtual address */\r
+    AddressValue = (*(__IO uint16_t*)Address);\r
+\r
+    /* Compare the read address with the virtual address */\r
+    if (AddressValue == VirtAddress)\r
+    {\r
+      /* Get content of Address-2 which is variable value */\r
+      *Data = (*(__IO uint16_t*)(Address - 2));\r
+\r
+      /* In case variable value is read, reset ReadStatus flag */\r
+      ReadStatus = 0;\r
+\r
+      break;\r
+    }\r
+    else\r
+    {\r
+      /* Next address location */\r
+      Address = Address - 4;\r
+    }\r
+  }\r
+\r
+  /* Return ReadStatus value: (0: variable exist, 1: variable doesn't exist) */\r
+  return ReadStatus;\r
+}\r
+\r
+/**\r
+  * @brief  Writes/upadtes variable data in EEPROM.\r
+  * @param  VirtAddress: Variable virtual address\r
+  * @param  Data: 16 bit data to be written\r
+  * @retval Success or error status:\r
+  *           - FLASH_COMPLETE: on success\r
+  *           - PAGE_FULL: if valid page is full\r
+  *           - NO_VALID_PAGE: if no valid page was found\r
+  *           - Flash error code: on write Flash error\r
+  */\r
+uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data)\r
+{\r
+  uint16_t Status = 0;\r
+\r
+  /* Write the variable virtual address and value in the EEPROM */\r
+  Status = EE_VerifyPageFullWriteVariable(VirtAddress, Data);\r
+\r
+  /* In case the EEPROM active page is full */\r
+  if (Status == PAGE_FULL)\r
+  {\r
+    /* Perform Page transfer */\r
+    Status = EE_PageTransfer(VirtAddress, Data);\r
+  }\r
+\r
+  /* Return last operation status */\r
+  return Status;\r
+}\r
+\r
+/**\r
+  * @brief  Erases PAGE0 and PAGE1 and writes VALID_PAGE header to PAGE0\r
+  * @param  None\r
+  * @retval Status of the last operation (Flash write or erase) done during\r
+  *         EEPROM formating\r
+  */\r
+static FLASH_Status EE_Format(void)\r
+{\r
+  FLASH_Status FlashStatus = FLASH_COMPLETE;\r
+\r
+  /* Erase Page0 */\r
+  FlashStatus = FLASH_ErasePage(PAGE0_BASE_ADDRESS);\r
+\r
+  /* If erase operation was failed, a Flash error code is returned */\r
+  if (FlashStatus != FLASH_COMPLETE)\r
+  {\r
+    return FlashStatus;\r
+  }\r
+\r
+  /* Set Page0 as valid page: Write VALID_PAGE at Page0 base address */\r
+  FlashStatus = FLASH_ProgramHalfWord(PAGE0_BASE_ADDRESS, VALID_PAGE);\r
+\r
+  /* If program operation was failed, a Flash error code is returned */\r
+  if (FlashStatus != FLASH_COMPLETE)\r
+  {\r
+    return FlashStatus;\r
+  }\r
+\r
+  /* Erase Page1 */\r
+  FlashStatus = FLASH_ErasePage(PAGE1_BASE_ADDRESS);\r
+\r
+  /* Return Page1 erase operation status */\r
+  return FlashStatus;\r
+}\r
+\r
+/**\r
+  * @brief  Find valid Page for write or read operation\r
+  * @param  Operation: operation to achieve on the valid page.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg READ_FROM_VALID_PAGE: read operation from valid page\r
+  *     @arg WRITE_IN_VALID_PAGE: write operation from valid page\r
+  * @retval Valid page number (PAGE0 or PAGE1) or NO_VALID_PAGE in case\r
+  *   of no valid page was found\r
+  */\r
+static uint16_t EE_FindValidPage(uint8_t Operation)\r
+{\r
+  uint16_t PageStatus0 = 6, PageStatus1 = 6;\r
+\r
+  /* Get Page0 actual status */\r
+  PageStatus0 = (*(__IO uint16_t*)PAGE0_BASE_ADDRESS);\r
+\r
+  /* Get Page1 actual status */\r
+  PageStatus1 = (*(__IO uint16_t*)PAGE1_BASE_ADDRESS);\r
+\r
+  /* Write or read operation */\r
+  switch (Operation)\r
+  {\r
+    case WRITE_IN_VALID_PAGE:   /* ---- Write operation ---- */\r
+      if (PageStatus1 == VALID_PAGE)\r
+      {\r
+        /* Page0 receiving data */\r
+        if (PageStatus0 == RECEIVE_DATA)\r
+        {\r
+          return PAGE0;         /* Page0 valid */\r
+        }\r
+        else\r
+        {\r
+          return PAGE1;         /* Page1 valid */\r
+        }\r
+      }\r
+      else if (PageStatus0 == VALID_PAGE)\r
+      {\r
+        /* Page1 receiving data */\r
+        if (PageStatus1 == RECEIVE_DATA)\r
+        {\r
+          return PAGE1;         /* Page1 valid */\r
+        }\r
+        else\r
+        {\r
+          return PAGE0;         /* Page0 valid */\r
+        }\r
+      }\r
+      else\r
+      {\r
+        return NO_VALID_PAGE;   /* No valid Page */\r
+      }\r
+\r
+    case READ_FROM_VALID_PAGE:  /* ---- Read operation ---- */\r
+      if (PageStatus0 == VALID_PAGE)\r
+      {\r
+        return PAGE0;           /* Page0 valid */\r
+      }\r
+      else if (PageStatus1 == VALID_PAGE)\r
+      {\r
+        return PAGE1;           /* Page1 valid */\r
+      }\r
+      else\r
+      {\r
+        return NO_VALID_PAGE ;  /* No valid Page */\r
+      }\r
+\r
+    default:\r
+      return PAGE0;             /* Page0 valid */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Verify if active page is full and Writes variable in EEPROM.\r
+  * @param  VirtAddress: 16 bit virtual address of the variable\r
+  * @param  Data: 16 bit data to be written as variable value\r
+  * @retval Success or error status:\r
+  *           - FLASH_COMPLETE: on success\r
+  *           - PAGE_FULL: if valid page is full\r
+  *           - NO_VALID_PAGE: if no valid page was found\r
+  *           - Flash error code: on write Flash error\r
+  */\r
+static uint16_t EE_VerifyPageFullWriteVariable(uint16_t VirtAddress, uint16_t Data)\r
+{\r
+  FLASH_Status FlashStatus = FLASH_COMPLETE;\r
+  uint16_t ValidPage = PAGE0;\r
+  uint32_t Address = 0x08010000, PageEndAddress = 0x080107FF;\r
+\r
+  /* Get valid Page for write operation */\r
+  ValidPage = EE_FindValidPage(WRITE_IN_VALID_PAGE);\r
+\r
+  /* Check if there is no valid page */\r
+  if (ValidPage == NO_VALID_PAGE)\r
+  {\r
+    return  NO_VALID_PAGE;\r
+  }\r
+\r
+  /* Get the valid Page start Address */\r
+  Address = (uint32_t)(EEPROM_START_ADDRESS + (uint32_t)(ValidPage * PAGE_SIZE));\r
+\r
+  /* Get the valid Page end Address */\r
+  PageEndAddress = (uint32_t)((EEPROM_START_ADDRESS - 2) + (uint32_t)((1 + ValidPage) * PAGE_SIZE));\r
+\r
+  /* Check each active page address starting from begining */\r
+  while (Address < PageEndAddress)\r
+  {\r
+    /* Verify if Address and Address+2 contents are 0xFFFFFFFF */\r
+    if ((*(__IO uint32_t*)Address) == 0xFFFFFFFF)\r
+    {\r
+      /* Set variable data */\r
+      FlashStatus = FLASH_ProgramHalfWord(Address, Data);\r
+      /* If program operation was failed, a Flash error code is returned */\r
+      if (FlashStatus != FLASH_COMPLETE)\r
+      {\r
+        return FlashStatus;\r
+      }\r
+      /* Set variable virtual address */\r
+      FlashStatus = FLASH_ProgramHalfWord(Address + 2, VirtAddress);\r
+      /* Return program operation status */\r
+      return FlashStatus;\r
+    }\r
+    else\r
+    {\r
+      /* Next address location */\r
+      Address = Address + 4;\r
+    }\r
+  }\r
+\r
+  /* Return PAGE_FULL in case the valid page is full */\r
+  return PAGE_FULL;\r
+}\r
+\r
+/**\r
+  * @brief  Transfers last updated variables data from the full Page to\r
+  *   an empty one.\r
+  * @param  VirtAddress: 16 bit virtual address of the variable\r
+  * @param  Data: 16 bit data to be written as variable value\r
+  * @retval Success or error status:\r
+  *           - FLASH_COMPLETE: on success\r
+  *           - PAGE_FULL: if valid page is full\r
+  *           - NO_VALID_PAGE: if no valid page was found\r
+  *           - Flash error code: on write Flash error\r
+  */\r
+static uint16_t EE_PageTransfer(uint16_t VirtAddress, uint16_t Data)\r
+{\r
+  FLASH_Status FlashStatus = FLASH_COMPLETE;\r
+  uint32_t NewPageAddress = 0x080103FF, OldPageAddress = 0x08010000;\r
+  uint16_t ValidPage = PAGE0, VarIdx = 0;\r
+  uint16_t EepromStatus = 0, ReadStatus = 0;\r
+\r
+  /* Get active Page for read operation */\r
+  ValidPage = EE_FindValidPage(READ_FROM_VALID_PAGE);\r
+\r
+  if (ValidPage == PAGE1)       /* Page1 valid */\r
+  {\r
+    /* New page address where variable will be moved to */\r
+    NewPageAddress = PAGE0_BASE_ADDRESS;\r
+\r
+    /* Old page address where variable will be taken from */\r
+    OldPageAddress = PAGE1_BASE_ADDRESS;\r
+  }\r
+  else if (ValidPage == PAGE0)  /* Page0 valid */\r
+  {\r
+    /* New page address where variable will be moved to */\r
+    NewPageAddress = PAGE1_BASE_ADDRESS;\r
+\r
+    /* Old page address where variable will be taken from */\r
+    OldPageAddress = PAGE0_BASE_ADDRESS;\r
+  }\r
+  else\r
+  {\r
+    return NO_VALID_PAGE;       /* No valid Page */\r
+  }\r
+\r
+  /* Set the new Page status to RECEIVE_DATA status */\r
+  FlashStatus = FLASH_ProgramHalfWord(NewPageAddress, RECEIVE_DATA);\r
+  /* If program operation was failed, a Flash error code is returned */\r
+  if (FlashStatus != FLASH_COMPLETE)\r
+  {\r
+    return FlashStatus;\r
+  }\r
+\r
+  /* Write the variable passed as parameter in the new active page */\r
+  EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddress, Data);\r
+  /* If program operation was failed, a Flash error code is returned */\r
+  if (EepromStatus != FLASH_COMPLETE)\r
+  {\r
+    return EepromStatus;\r
+  }\r
+\r
+  /* Transfer process: transfer variables from old to the new active page */\r
+  for (VarIdx = 0; VarIdx < NumbOfVar; VarIdx++)\r
+  {\r
+    if (VirtAddVarTab[VarIdx] != VirtAddress)  /* Check each variable except the one passed as parameter */\r
+    {\r
+      /* Read the other last variable updates */\r
+      ReadStatus = EE_ReadVariable(VirtAddVarTab[VarIdx], &DataVar);\r
+      /* In case variable corresponding to the virtual address was found */\r
+      if (ReadStatus != 0x1)\r
+      {\r
+        /* Transfer the variable to the new active page */\r
+        EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddVarTab[VarIdx], DataVar);\r
+        /* If program operation was failed, a Flash error code is returned */\r
+        if (EepromStatus != FLASH_COMPLETE)\r
+        {\r
+          return EepromStatus;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  /* Erase the old Page: Set old Page status to ERASED status */\r
+  FlashStatus = FLASH_ErasePage(OldPageAddress);\r
+  /* If erase operation was failed, a Flash error code is returned */\r
+  if (FlashStatus != FLASH_COMPLETE)\r
+  {\r
+    return FlashStatus;\r
+  }\r
+\r
+  /* Set new Page status to VALID_PAGE status */\r
+  FlashStatus = FLASH_ProgramHalfWord(NewPageAddress, VALID_PAGE);\r
+  /* If program operation was failed, a Flash error code is returned */\r
+  if (FlashStatus != FLASH_COMPLETE)\r
+  {\r
+    return FlashStatus;\r
+  }\r
+\r
+  /* Return last operation flash status */\r
+  return FlashStatus;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
diff --git a/Eeprom.h b/Eeprom.h
new file mode 100644 (file)
index 0000000..c2a420c
--- /dev/null
+++ b/Eeprom.h
@@ -0,0 +1,99 @@
+/**\r
+  ******************************************************************************\r
+  * @file    EEPROM_Emulation/inc/eeprom.h \r
+  * @author  MCD Application Team\r
+  * @version V3.1.0\r
+  * @date    07/27/2009\r
+  * @brief   This file contains all the functions prototypes for the EEPROM \r
+  *          emulation firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __EEPROM_H\r
+#define __EEPROM_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Define the STM32F10Xxx Flash page size depending on the used STM32 device */\r
+#if defined (STM32F10X_LD) || defined (STM32F10X_MD)\r
+  #define PAGE_SIZE  (uint16_t)0x400  /* Page size = 1KByte */\r
+#elif defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+  #define PAGE_SIZE  (uint16_t)0x800  /* Page size = 2KByte */\r
+#endif\r
+\r
+/* EEPROM start address in Flash */\r
+#define EEPROM_START_ADDRESS    ((uint32_t)0x0800C000) /* EEPROM emulation start address:\r
+                                                  after 64KByte of used Flash memory */\r
+\r
+/* Pages 0 and 1 base and end addresses */\r
+#define PAGE0_BASE_ADDRESS      ((uint32_t)(EEPROM_START_ADDRESS + 0x000))\r
+#define PAGE0_END_ADDRESS       ((uint32_t)(EEPROM_START_ADDRESS + (PAGE_SIZE - 1)))\r
+\r
+#define PAGE1_BASE_ADDRESS      ((uint32_t)(EEPROM_START_ADDRESS + PAGE_SIZE))\r
+#define PAGE1_END_ADDRESS       ((uint32_t)(EEPROM_START_ADDRESS + (2 * PAGE_SIZE - 1)))\r
+\r
+/* Used Flash pages for EEPROM emulation */\r
+#define PAGE0                   ((uint16_t)0x0000)\r
+#define PAGE1                   ((uint16_t)0x0001)\r
+\r
+/* No valid page define */\r
+#define NO_VALID_PAGE           ((uint16_t)0x00AB)\r
+\r
+/* Page status definitions */\r
+#define ERASED                  ((uint16_t)0xFFFF)     /* PAGE is empty */\r
+#define RECEIVE_DATA            ((uint16_t)0xEEEE)     /* PAGE is marked to receive data */\r
+#define VALID_PAGE              ((uint16_t)0x0000)     /* PAGE containing valid data */\r
+\r
+/* Valid pages in read and write defines */\r
+#define READ_FROM_VALID_PAGE    ((uint8_t)0x00)\r
+#define WRITE_IN_VALID_PAGE     ((uint8_t)0x01)\r
+\r
+/* Page full define */\r
+#define PAGE_FULL               ((uint8_t)0x80)\r
+\r
+/* Variables' number */\r
+#define NumbOfVar               ((uint8_t)20)\r
+\r
+/* Virtual address defined by the user: 0xFFFF value is prohibited */\r
+extern uint16_t VirtAddVarTab[NumbOfVar];\r
+\r
+// Define virtual EEPROM addresses to be used here\r
+enum {\r
+       Addr_TimeBase           = 0,\r
+       Addr_HPos,\r
+       Addr_Vsen,\r
+       Addr_Cpl,\r
+       Addr_Vpos,\r
+       Addr_VPosOfs,\r
+       Addr_TrigMode,\r
+       Addr_TrigEdge,\r
+       Addr_TrigLvl,\r
+       Addr_TrigPos,\r
+       Addr_RecLen,\r
+       Addr_SettingStatus,\r
+       \r
+       };\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+uint16_t EE_Init(void);\r
+uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t* Data);\r
+uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data);\r
+\r
+#endif /* __EEPROM_H */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
diff --git a/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
new file mode 100644 (file)
index 0000000..56fddc5
--- /dev/null
@@ -0,0 +1,784 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.c\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version  V1.30\r
+ * @date     30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
+\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+  mrs r0, psp\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  msr psp, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+  mrs r0, msp\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+  msr msp, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param   value  value to reverse\r
+ * @return         reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+  rev16 r0, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param   value  value to reverse\r
+ * @return         reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+  revsh r0, r0\r
+  bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+  clrex\r
+}\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t  __get_BASEPRI(void)\r
+{\r
+  mrs r0, basepri\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  msr basepri, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+  mrs r0, primask\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  msr primask, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t  __get_FAULTMASK(void)\r
+{\r
+  mrs r0, faultmask\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  msr faultmask, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+  mrs r0, control\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+  msr control, r0\r
+  bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+  __ASM("mrs r0, psp");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM("msr psp, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+  __ASM("mrs r0, msp");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM("msr msp, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+  __ASM("rev16 r0, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+  __ASM("rbit r0, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (8 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+  __ASM("ldrexb r0, [r0]");\r
+  __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (16 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+  __ASM("ldrexh r0, [r0]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (32 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+  __ASM("ldrex r0, [r0]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (8 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+  __ASM("strexb r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (16 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+  __ASM("strexh r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (32 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+  __ASM("strex r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, psp\n\t" \r
+                  "MOV r0, %0 \n\t"\r
+                  "BX  lr     \n\t"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp, %0\n\t"\r
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, msp\n\t" \r
+                  "MOV r0, %0 \n\t"\r
+                  "BX  lr     \n\t"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp, %0\n\t"\r
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (8 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+    uint8_t result=0;\r
+  \r
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (16 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+    uint16_t result=0;\r
+  \r
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (32 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+    uint32_t result=0;\r
+  \r
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (8 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (16 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (32 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
diff --git a/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h b/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
new file mode 100644 (file)
index 0000000..2b6b51a
--- /dev/null
@@ -0,0 +1,1818 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.h\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version  V1.30\r
+ * @date     30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ *   - Error 10: \n\r
+ *     register uint32_t __regBasePri         __asm("basepri"); \n\r
+ *     Error 10: Expecting ';'\r
+ * .\r
+ *   - Error 530: \n\r
+ *     return(__regBasePri); \n\r
+ *     Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ *   - Error 550: \n\r
+ *     __regBasePri = (basePri & 0x1ff); \n\r
+ *     Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ *   - Error 754: \n\r
+ *     uint32_t RESERVED0[24]; \n\r
+ *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ *   - Error 750: \n\r
+ *     #define __CM3_CORE_H__ \n\r
+ *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ *   - Error 528: \n\r
+ *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ *   - Error 751: \n\r
+ *     } InterruptType_Type; \n\r
+ *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note:  To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10  */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+  This file defines all structures and symbols for CMSIS core:\r
+    - CMSIS version number\r
+    - Cortex-M core registers and bitfields\r
+    - Cortex-M core peripheral base address\r
+  @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */\r
+\r
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */\r
+\r
+#include <stdint.h>                           /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+  #include <intrinsics.h>                     /* IAR Intrinsics   */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+  #define     __I     volatile                /*!< defines 'read only' permissions      */\r
+#else\r
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */\r
+#endif\r
+#define     __O     volatile                  /*!< defines 'write only' permissions     */\r
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */\r
+       uint32_t RESERVED0[24];                                   \r
+  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */\r
+       uint32_t RSERVED1[24];                                    \r
+  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */\r
+       uint32_t RESERVED2[24];                                   \r
+  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */\r
+       uint32_t RESERVED3[24];                                   \r
+  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */\r
+       uint32_t RESERVED4[56];                                   \r
+  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */\r
+       uint32_t RESERVED5[644];                                  \r
+  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */\r
+}  NVIC_Type;                                               \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+  memory mapped structure for System Control Block (SCB)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */\r
+  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */\r
+  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */\r
+  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */\r
+  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */\r
+  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */\r
+  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */\r
+  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */\r
+  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */\r
+  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */\r
+  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */\r
+  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */\r
+  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */\r
+  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */\r
+  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */\r
+  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */\r
+  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */\r
+  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */\r
+} SCB_Type;                                                \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+                                     \r
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+  memory mapped structure for SysTick\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+  memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __O  union  \r
+  {\r
+    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */\r
+    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */\r
+    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */\r
+  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */\r
+       uint32_t RESERVED0[864];                                 \r
+  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */\r
+       uint32_t RESERVED1[15];                                  \r
+  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */\r
+       uint32_t RESERVED2[15];                                  \r
+  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */\r
+       uint32_t RESERVED3[29];                                  \r
+  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */\r
+  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */\r
+  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */\r
+       uint32_t RESERVED4[43];                                  \r
+  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */\r
+  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */\r
+       uint32_t RESERVED5[6];                                   \r
+  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */\r
+  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */\r
+  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */\r
+  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */\r
+  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */\r
+  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */\r
+  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */\r
+  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */\r
+  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */\r
+  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */\r
+  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */\r
+  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */\r
+} ITM_Type;                                                \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+  memory mapped structure for Interrupt Type\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+       uint32_t RESERVED0;\r
+  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */\r
+#else\r
+       uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+  memory mapped structure for Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */\r
+  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */\r
+  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */\r
+  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */\r
+  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */\r
+  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */\r
+  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */\r
+  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */\r
+  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */\r
+  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;                                                \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+  memory mapped structure for Core Debug Register\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */\r
+  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */\r
+  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */\r
+  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */\r
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */\r
+\r
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */\r
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */\r
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */\r
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */\r
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+  #define MPU_BASE    &