3 Copyright 2004 Broadcom Corp. All Rights Reserved.
5 This program is free software; you can distribute it and/or modify it
6 under the terms of the GNU General Public License (Version 2) as
7 published by the Free Software Foundation.
9 This program is distributed in the hope it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 You should have received a copy of the GNU General Public License along
15 with this program; if not, write to the Free Software Foundation, Inc.,
16 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 // bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition
26 /* Memory window in internal system bus address space */
27 #define BCM_PCI_MEM_BASE 0x10000000
28 #define BCM_CB_MEM_BASE 0x11000000
29 /* IO window in internal system bus address space */
30 #define BCM_PCI_IO_BASE 0x12000000
32 #define BCM_PCI_ADDR_MASK 0x1fffffff
34 /* Memory window size (range) */
35 #define BCM_PCI_MEM_SIZE_16MB 0x01000000
36 #define BCM_CB_MEM_SIZE_16MB 0x01000000
37 /* IO window size (range) */
38 #define BCM_PCI_IO_SIZE_64KB 0x00010000
40 /* PCI Configuration and I/O space acesss */
41 #define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) )
43 /* fake USB PCI slot */
44 #define USB_HOST_SLOT 9
45 #define USB20_HOST_SLOT 10
46 #define USB_BAR0_MEM_SIZE 0x0100
48 #define BCM_HOST_MEM_SPACE1 0x10000000
49 #define BCM_HOST_MEM_SPACE2 0x00000000
52 * EBI bus clock is 33MHz and share with PCI bus
53 * each clock cycle is 30ns.
55 /* attribute memory access wait cnt for 4306 */
56 #define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns
57 #define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns
58 #define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
59 #define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns
61 /* common memory access wait cnt for 4306 */
62 #define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns
63 #define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns
64 #define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
65 #define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns
67 #define PCCARD_VCC_MASK 0x00070000 // Mask Reset also
68 #define PCCARD_VCC_33V 0x00010000
69 #define PCCARD_VCC_50V 0x00020000
72 MPI_CARDTYPE_NONE, // No Card in slot
73 MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot
74 MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot
77 #define CARDBUS_SLOT 0 // Slot 0 is default for CardBus
79 #define pcmciaAttrOffset 0x00200000
80 #define pcmciaMemOffset 0x00000000
81 // Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
82 #define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000)
83 // Base Address is that mapped into the MPI ChipSelect registers.
84 // UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
85 #define pcmciaBase 0xbf000000
86 #define pcmciaAttr (pcmciaAttrOffset | pcmciaBase)
87 #define pcmciaMem (pcmciaMemOffset | pcmciaBase)
88 #define pcmciaIo (pcmciaIoOffset | pcmciaBase)