2 * linux/include/asm-arm/arch-ebsa285/time.h
4 * Copyright (C) 1998 Russell King.
5 * Copyright (C) 1998 Phil Blundell
7 * CATS has a real-time clock, though the evaluation board doesn't.
10 * 21-Mar-1998 RMK Created
11 * 27-Aug-1998 PJB CATS support
12 * 28-Dec-1998 APH Made leds optional
13 * 20-Jan-1999 RMK Started merge of EBSA285, CATS and NetWinder
14 * 16-Mar-1999 RMK More support for EBSA285-like machines with RTCs in
17 #define RTC_PORT(x) (rtc_base+(x))
18 #define RTC_ALWAYS_BCD 0
20 #include <linux/timex.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/sched.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/bcd.h>
27 #include <asm/hardware/dec21285.h>
29 #include <asm/hardware.h>
32 #include <asm/mach-types.h>
34 #include <asm/hardware/clps7111.h>
36 #include <asm/mach/time.h>
40 #define mSEC_10_from_14 ((14318180 + 100) / 200)
42 static unsigned long isa_gettimeoffset(void)
46 static int count_p = (mSEC_10_from_14/6); /* for the first call after boot */
47 static unsigned long jiffies_p = 0;
50 * cache volatile jiffies temporarily; we have IRQs turned off.
52 unsigned long jiffies_t;
54 /* timer count may underflow right here */
55 outb_p(0x00, 0x43); /* latch the count ASAP */
57 count = inb_p(0x40); /* read the latched count */
60 * We do this guaranteed double memory access instead of a _p
61 * postfix in the previous port access. Wheee, hackady hack
65 count |= inb_p(0x40) << 8;
67 /* Detect timer underflows. If we haven't had a timer tick since
68 the last time we were called, and time is apparently going
69 backwards, the counter must have wrapped during this routine. */
70 if ((jiffies_t == jiffies_p) && (count > count_p))
71 count -= (mSEC_10_from_14/6);
73 jiffies_p = jiffies_t;
77 count = (((mSEC_10_from_14/6)-1) - count) * (tick_nsec / 1000);
78 count = (count + (mSEC_10_from_14/6)/2) / (mSEC_10_from_14/6);
84 isa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
91 static unsigned long __init get_isa_cmos_time(void)
93 unsigned int year, mon, day, hour, min, sec;
96 // check to see if the RTC makes sense.....
97 if ((CMOS_READ(RTC_VALID) & RTC_VRT) == 0)
98 return mktime(1970, 1, 1, 0, 0, 0);
100 /* The Linux interpretation of the CMOS clock register contents:
101 * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
102 * RTC registers show the second which has precisely just started.
103 * Let's hope other operating systems interpret the RTC the same way.
105 /* read RTC exactly on falling edge of update flag */
106 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
107 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
110 for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */
111 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
114 do { /* Isn't this overkill ? UIP above should guarantee consistency */
115 sec = CMOS_READ(RTC_SECONDS);
116 min = CMOS_READ(RTC_MINUTES);
117 hour = CMOS_READ(RTC_HOURS);
118 day = CMOS_READ(RTC_DAY_OF_MONTH);
119 mon = CMOS_READ(RTC_MONTH);
120 year = CMOS_READ(RTC_YEAR);
121 } while (sec != CMOS_READ(RTC_SECONDS));
123 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
131 if ((year += 1900) < 1970)
133 return mktime(year, mon, day, hour, min, sec);
137 set_isa_cmos_time(void)
140 int real_seconds, real_minutes, cmos_minutes;
141 unsigned char save_control, save_freq_select;
142 unsigned long nowtime = xtime.tv_sec;
144 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
145 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
147 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
148 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
150 cmos_minutes = CMOS_READ(RTC_MINUTES);
151 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
152 BCD_TO_BIN(cmos_minutes);
155 * since we're only adjusting minutes and seconds,
156 * don't interfere with hour overflow. This avoids
157 * messing with unknown time zones but requires your
158 * RTC not to be off by more than 15 minutes
160 real_seconds = nowtime % 60;
161 real_minutes = nowtime / 60;
162 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
163 real_minutes += 30; /* correct for half hour time zone */
166 if (abs(real_minutes - cmos_minutes) < 30) {
167 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
168 BIN_TO_BCD(real_seconds);
169 BIN_TO_BCD(real_minutes);
171 CMOS_WRITE(real_seconds,RTC_SECONDS);
172 CMOS_WRITE(real_minutes,RTC_MINUTES);
176 /* The following flags have to be released exactly in this order,
177 * otherwise the DS12887 (popular MC146818A clone with integrated
178 * battery and quartz) will not reset the oscillator and will not
179 * update precisely 500 ms later. You won't find this mentioned in
180 * the Dallas Semiconductor data sheets, but who believes data
181 * sheets anyway ... -- Markus Kuhn
183 CMOS_WRITE(save_control, RTC_CONTROL);
184 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
190 static unsigned long timer1_latch;
192 static unsigned long timer1_gettimeoffset (void)
194 unsigned long value = timer1_latch - *CSR_TIMER1_VALUE;
196 return ((tick_nsec / 1000) * value) / timer1_latch;
200 timer1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
209 static struct irqaction footbridge_timer_irq = {
210 .flags = SA_INTERRUPT
214 * Set up timer interrupt.
216 void __init footbridge_init_time(void)
218 if (machine_is_co285() ||
219 machine_is_personal_server())
221 * Add-in 21285s shouldn't access the RTC
233 reg_d = CMOS_READ(RTC_REG_D);
236 * make sure the divider is set
238 CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_REG_A);
242 * (24 hour mode, update enabled)
244 reg_b = CMOS_READ(RTC_REG_B) & 0x7f;
246 CMOS_WRITE(reg_b, RTC_REG_B);
248 if ((CMOS_READ(RTC_REG_A) & 0x7f) == RTC_REF_CLCK_32KHZ &&
249 CMOS_READ(RTC_REG_B) == reg_b) {
253 * We have a RTC. Check the battery
255 if ((reg_d & 0x80) == 0)
256 printk(KERN_WARNING "RTC: *** warning: CMOS battery bad\n");
259 tv.tv_sec = get_isa_cmos_time();
260 do_settimeofday(&tv);
261 set_rtc = set_isa_cmos_time;
266 if (machine_is_ebsa285() ||
267 machine_is_co285() ||
268 machine_is_personal_server()) {
269 gettimeoffset = timer1_gettimeoffset;
271 timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
274 *CSR_TIMER1_LOAD = timer1_latch;
275 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16;
277 footbridge_timer_irq.name = "Timer1 Timer Tick";
278 footbridge_timer_irq.handler = timer1_interrupt;
280 setup_irq(IRQ_TIMER1, &footbridge_timer_irq);
283 /* enable PIT timer */
284 /* set for periodic (4) and LSB/MSB write (0x30) */
286 outb((mSEC_10_from_14/6) & 0xFF, 0x40);
287 outb((mSEC_10_from_14/6) >> 8, 0x40);
289 gettimeoffset = isa_gettimeoffset;
291 footbridge_timer_irq.name = "ISA Timer Tick";
292 footbridge_timer_irq.handler = isa_timer_interrupt;
294 setup_irq(IRQ_ISA_TIMER, &footbridge_timer_irq);