kernel/linux/arch/arm/mach-omap/fpga.c

   1 /*
   2  * linux/arch/arm/mach-omap/fpga.c
   3  *
   4  * Interrupt handler for OMAP-1510 Innovator FPGA
   5  *
   6  * Copyright (C) 2001 RidgeRun, Inc.
   7  * Author: Greg Lonnon <glonnon@ridgerun.com>
   8  *
   9  * Copyright (C) 2002 MontaVista Software, Inc.
  10  *
  11  * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
  12  * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <linux/config.h>
  20 #include <linux/types.h>
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>
  24 #include <linux/errno.h>
  25
  26 #include <asm/hardware.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/mach/irq.h>
  30
  31 #include <asm/arch/fpga.h>
  32 #include <asm/arch/gpio.h>
  33
  34 unsigned char fpga_read(int reg)
  35 {
  36         return __raw_readb(reg);
  37 }
  38
  39 void fpga_write(unsigned char val, int reg)
  40 {
  41         __raw_writeb(val, reg);
  42 }
  43
  44 static void fpga_mask_irq(unsigned int irq)
  45 {
  46         irq -= IH_FPGA_BASE;
  47
  48         if (irq < 8)
  49                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
  50                               & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
  51         else if (irq < 16)
  52                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
  53                               & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
  54         else
  55                 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
  56                               & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
  57 }
  58
  59
  60 static inline u32 get_fpga_unmasked_irqs(void)
  61 {
  62         return
  63                 ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
  64                   __raw_readb(OMAP1510_FPGA_IMR_LO))) |
  65                 ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
  66                   __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
  67                 ((__raw_readb(INNOVATOR_FPGA_ISR2) &
  68                   __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
  69 }
  70
  71
  72 static void fpga_ack_irq(unsigned int irq)
  73 {
  74         /* Don't need to explicitly ACK FPGA interrupts */
  75 }
  76
  77 static void fpga_unmask_irq(unsigned int irq)
  78 {
  79         irq -= IH_FPGA_BASE;
  80
  81         if (irq < 8)
  82                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
  83                      OMAP1510_FPGA_IMR_LO);
  84         else if (irq < 16)
  85                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
  86                               | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
  87         else
  88                 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
  89                               | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
  90 }
  91
  92 static void fpga_mask_ack_irq(unsigned int irq)
  93 {
  94         fpga_mask_irq(irq);
  95         fpga_ack_irq(irq);
  96 }
  97
  98 void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
  99                               struct pt_regs *regs)
 100 {
 101         struct irqdesc *d;
 102         u32 stat;
 103         int fpga_irq;
 104
 105         /*
 106          * Acknowledge the parent IRQ.
 107          */
 108         desc->chip->ack(irq);
 109
 110         for (;;) {
 111                 stat = get_fpga_unmasked_irqs();
 112
 113                 if (!stat) {
 114                         break;
 115                 }
 116
 117                 for (fpga_irq = IH_FPGA_BASE;
 118                         (fpga_irq < (IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
 119                         fpga_irq++, stat >>= 1) {
 120                         if (stat & 1) {
 121                                 d = irq_desc + fpga_irq;
 122                                 d->handle(fpga_irq, d, regs);
 123                                 desc->chip->unmask(irq);
 124                         }
 125                 }
 126         }
 127 }
 128
 129 static struct irqchip omap_fpga_irq_ack = {
 130         .ack            = fpga_mask_ack_irq,
 131         .mask           = fpga_mask_irq,
 132         .unmask         = fpga_unmask_irq,
 133 };
 134
 135
 136 static struct irqchip omap_fpga_irq = {
 137         .ack            = fpga_ack_irq,
 138         .mask           = fpga_mask_irq,
 139         .unmask         = fpga_unmask_irq,
 140 };
 141
 142 /*
 143  * All of the FPGA interrupt request inputs except for the touchscreen are
 144  * edge-sensitive; the touchscreen is level-sensitive.  The edge-sensitive
 145  * interrupts are acknowledged as a side-effect of reading the interrupt
 146  * status register from the FPGA.  The edge-sensitive interrupt inputs
 147  * cause a problem with level interrupt requests, such as Ethernet.  The
 148  * problem occurs when a level interrupt request is asserted while its
 149  * interrupt input is masked in the FPGA, which results in a missed
 150  * interrupt.
 151  *
 152  * In an attempt to workaround the problem with missed interrupts, the
 153  * mask_ack routine for all of the FPGA interrupts has been changed from
 154  * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
 155  * being serviced is left unmasked.  We can do this because the FPGA cascade
 156  * interrupt is installed with the SA_INTERRUPT flag, which leaves all
 157  * interrupts masked at the CPU while an FPGA interrupt handler executes.
 158  *
 159  * Limited testing indicates that this workaround appears to be effective
 160  * for the smc9194 Ethernet driver used on the Innovator.  It should work
 161  * on other FPGA interrupts as well, but any drivers that explicitly mask
 162  * interrupts at the interrupt controller via disable_irq/enable_irq
 163  * could pose a problem.
 164  */
 165 void fpga_init_irq(void)
 166 {
 167         int i;
 168
 169         __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
 170         __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
 171         __raw_writeb(0, INNOVATOR_FPGA_IMR2);
 172
 173         for (i = IH_FPGA_BASE; i < (IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
 174
 175                 if (i == INT_FPGA_TS) {
 176                         /*
 177                          * The touchscreen interrupt is level-sensitive, so
 178                          * we'll use the regular mask_ack routine for it.
 179                          */
 180                         set_irq_chip(i, &omap_fpga_irq_ack);
 181                 }
 182                 else {
 183                         /*
 184                          * All FPGA interrupts except the touchscreen are
 185                          * edge-sensitive, so we won't mask them.
 186                          */
 187                         set_irq_chip(i, &omap_fpga_irq);
 188                 }
 189
 190                 set_irq_handler(i, do_level_IRQ);
 191                 set_irq_flags(i, IRQF_VALID);
 192         }
 193
 194         /*
 195          * The FPGA interrupt line is connected to GPIO13. Claim this pin for
 196          * the ARM.
 197          *
 198          * NOTE: For general GPIO/MPUIO access and interrupts, please see
 199          * gpio.[ch]
 200          */
 201         omap_request_gpio(13);
 202         omap_set_gpio_direction(13, 1);
 203         omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
 204         set_irq_chained_handler(INT_FPGA, innovator_fpga_IRQ_demux);
 205 }
 206
 207 EXPORT_SYMBOL(fpga_init_irq);
 208 EXPORT_SYMBOL(fpga_read);
 209 EXPORT_SYMBOL(fpga_write);