kernel/linux/arch/sh/mm/cache-sh3.c

   1 /* $Id: cache-sh3.c,v 1.9 2004/05/02 01:46:30 sugioka Exp $
   2  *
   3  *  linux/arch/sh/mm/cache-sh3.c
   4  *
   5  * Copyright (C) 1999, 2000  Niibe Yutaka
   6  * Copyright (C) 2002 Paul Mundt
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/mman.h>
  11 #include <linux/mm.h>
  12 #include <linux/threads.h>
  13 #include <asm/addrspace.h>
  14 #include <asm/page.h>
  15 #include <asm/pgtable.h>
  16 #include <asm/processor.h>
  17 #include <asm/cache.h>
  18 #include <asm/io.h>
  19 #include <asm/uaccess.h>
  20 #include <asm/pgalloc.h>
  21 #include <asm/mmu_context.h>
  22 #include <asm/cacheflush.h>
  23
  24 int __init detect_cpu_and_cache_system(void)
  25 {
  26         unsigned long addr0, addr1, data0, data1, data2, data3;
  27
  28         jump_to_P2();
  29         /*
  30          * Check if the entry shadows or not.
  31          * When shadowed, it's 128-entry system.
  32          * Otherwise, it's 256-entry system.
  33          */
  34         addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
  35         addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
  36
  37         /* First, write back & invalidate */
  38         data0  = ctrl_inl(addr0);
  39         ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
  40         data1  = ctrl_inl(addr1);
  41         ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
  42
  43         /* Next, check if there's shadow or not */
  44         data0 = ctrl_inl(addr0);
  45         data0 ^= SH_CACHE_VALID;
  46         ctrl_outl(data0, addr0);
  47         data1 = ctrl_inl(addr1);
  48         data2 = data1 ^ SH_CACHE_VALID;
  49         ctrl_outl(data2, addr1);
  50         data3 = ctrl_inl(addr0);
  51
  52         /* Lastly, invaliate them. */
  53         ctrl_outl(data0&~SH_CACHE_VALID, addr0);
  54         ctrl_outl(data2&~SH_CACHE_VALID, addr1);
  55
  56         back_to_P1();
  57
  58         cpu_data->dcache.ways           = 4;
  59         cpu_data->dcache.entry_shift    = 4;
  60         cpu_data->dcache.linesz         = L1_CACHE_BYTES;
  61         cpu_data->dcache.flags          = 0;
  62
  63         /*
  64          * 7709A/7729 has 16K cache (256-entry), while 7702 has only
  65          * 2K(direct) 7702 is not supported (yet)
  66          */
  67         if (data0 == data1 && data2 == data3) { /* Shadow */
  68                 cpu_data->dcache.way_incr       = (1 << 11);
  69                 cpu_data->dcache.entry_mask     = 0x7f0;
  70                 cpu_data->dcache.sets           = 128;
  71                 cpu_data->type = CPU_SH7708;
  72
  73                 cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC;
  74         } else {                                /* 7709A or 7729  */
  75                 cpu_data->dcache.way_incr       = (1 << 12);
  76                 cpu_data->dcache.entry_mask     = 0xff0;
  77                 cpu_data->dcache.sets           = 256;
  78                 cpu_data->type = CPU_SH7729;
  79         }
  80
  81         /*
  82          * SH-3 doesn't have separate caches
  83          */
  84         cpu_data->dcache.flags |= SH_CACHE_COMBINED;
  85         cpu_data->icache = cpu_data->dcache;
  86
  87         return 0;
  88 }
  89
  90 /*
  91  * Write back the dirty D-caches, but not invalidate them.
  92  *
  93  * Is this really worth it, or should we just alias this routine
  94  * to __flush_purge_region too?
  95  *
  96  * START: Virtual Address (U0, P1, or P3)
  97  * SIZE: Size of the region.
  98  */
  99
 100 void __flush_wback_region(void *start, int size)
 101 {
 102         unsigned long v, j;
 103         unsigned long begin, end;
 104         unsigned long flags;
 105
 106         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
 107         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
 108                 & ~(L1_CACHE_BYTES-1);
 109
 110         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
 111                 unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY;
 112                 for (j = 0; j < cpu_data->dcache.ways; j++) {
 113                         unsigned long data, addr, p;
 114
 115                         p = __pa(v);
 116                         addr = addrstart | (v & cpu_data->dcache.entry_mask);
 117                         local_irq_save(flags);
 118                         data = ctrl_inl(addr);
 119
 120                         if ((data & CACHE_PHYSADDR_MASK) ==
 121                             (p & CACHE_PHYSADDR_MASK)) {
 122                                 data &= ~SH_CACHE_UPDATED;
 123                                 ctrl_outl(data, addr);
 124                                 local_irq_restore(flags);
 125                                 break;
 126                         }
 127                         local_irq_restore(flags);
 128                         addrstart += cpu_data->dcache.way_incr;
 129                 }
 130         }
 131 }
 132
 133 /*
 134  * Write back the dirty D-caches and invalidate them.
 135  *
 136  * START: Virtual Address (U0, P1, or P3)
 137  * SIZE: Size of the region.
 138  */
 139 void __flush_purge_region(void *start, int size)
 140 {
 141         unsigned long v;
 142         unsigned long begin, end;
 143
 144         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
 145         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
 146                 & ~(L1_CACHE_BYTES-1);
 147
 148         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
 149                 unsigned long data, addr;
 150
 151                 data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
 152                 addr = CACHE_OC_ADDRESS_ARRAY |
 153                         (v & cpu_data->dcache.entry_mask) | SH_CACHE_ASSOC;
 154                 ctrl_outl(data, addr);
 155         }
 156 }
 157
 158 /*
 159  * No write back please
 160  *
 161  * Except I don't think there's any way to avoid the writeback. So we
 162  * just alias it to __flush_purge_region(). dwmw2.
 163  */
 164 void __flush_invalidate_region(void *start, int size)
 165         __attribute__((alias("__flush_purge_region")));