fxload fx2lp dev board

[fx2fw-sdcc] / hw_basic.c

diff --git a/hw_basic.c b/hw_basic.c
index 2014fbe..69867dc 100644 (file)
--- a/hw_basic.c
+++ b/hw_basic.c
@@ -21,22 +21,26 @@
 #include "delay.h"\r
 \r
 //-----------------------------------------------------------------------------\r
+// comment out (undefine!) if you don't want PS, AS or OE signals\r
 \r
 #define HAVE_PS_MODE 1\r
 #define HAVE_AS_MODE 1\r
 #define HAVE_OE_LED  1\r
 \r
+// comment in (define!) if you want outputs disabled when possible\r
+//#define HAVE_OENABLE 1\r
+\r
 //-----------------------------------------------------------------------------\r
 \r
 /* JTAG TCK, AS/PS DCLK */\r
 \r
-sbit at 0xA2          TCK; /* Port C.0 */\r
+sbit at 0xA2          TCK; /* Port C.2 */\r
 #define bmTCKOE       bmBIT2\r
 #define SetTCK(x)     do{TCK=(x);}while(0)\r
 \r
 /* JTAG TDI, AS ASDI, PS DATA0 */\r
 \r
-sbit at 0xA0          TDI; /* Port C.2 */\r
+sbit at 0xA0          TDI; /* Port C.0 */\r
 #define bmTDIOE       bmBIT0\r
 #define SetTDI(x)     do{TDI=(x);}while(0)\r
 \r
@@ -53,7 +57,7 @@ sbit at 0xA1          TDO; /* Port C.1 */
 #define GetTDO(x)     TDO\r
 \r
 /* JTAG ENABLE */\r
-sbit JTAG_EN = 0xA0+7;\r
+sbit JTAG_EN = 0xA7; /* Port C.7 */\r
 #define bmJTAG_EN bmBIT7\r
 \r
 //-----------------------------------------------------------------------------\r
@@ -69,7 +73,7 @@ sbit JTAG_EN = 0xA0+7;
 #else\r
 \r
   #define bmASDOOE    0\r
-  #define GetASDO(x)  0\r
+  #define GetASDO(x)  1\r
 \r
 #endif\r
 \r
@@ -138,6 +142,15 @@ void ProgIO_Init(void)
   /* The following code depends on your actual circuit design.\r
      Make required changes _before_ you try the code! */\r
   \r
+  // set the CPU clock to 48MHz, enable clock output to FPGA\r
+  CPUCS = bmCLKOE | bmCLKSPD1;\r
+\r
+   // put the system in FIFO mode by default\r
+   // internal clock source at 48Mhz, drive output pin, synchronous mode\r
+   // NOTE: Altera USB-Blaster does not work in another mode\r
+   IFCONFIG =  bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;\r
+   IFCONFIG |= bmASYNC | bmIFCFG1 | bmIFCFG0;\r
+\r
    // set port C output enable (so we can handle the JTAG enable signal)\r
    OEC = (1 << 7);\r
 \r
@@ -148,17 +161,8 @@ void ProgIO_Init(void)
    // more than 100ma)\r
    IOE = (1 << 6);\r
 \r
-   // set the CPU clock to 48MHz\r
-   CPUCS = bmCLKSPD1;\r
-\r
    // activate JTAG outputs on Port C\r
    OEC = bmTDIOE | bmTCKOE | bmTMSOE | bmJTAG_EN;\r
-\r
-   // put the system in FIFO mode by default\r
-   // internal clock source at 48Mhz, drive output pin, synchronous mode\r
-   // NOTE: Altera USB-Blaster does not work in another mode\r
-   IFCONFIG =  bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;\r
-   IFCONFIG |= bmASYNC | bmIFCFG1 | bmIFCFG0;\r
 }\r
 \r
 void ProgIO_Set_State(unsigned char d)\r
@@ -170,7 +174,7 @@ void ProgIO_Set_State(unsigned char d)
    * d.2 => nCE (only #ifdef HAVE_AS_MODE)\r
    * d.3 => nCS (only #ifdef HAVE_AS_MODE)\r
    * d.4 => TDI\r
-   * d.6 => LED / Output Enable\r
+   * d.5 => LED / Output Enable\r
    */\r
 \r
   SetTCK((d & bmBIT0) ? 1 : 0);\r
@@ -187,14 +191,14 @@ void ProgIO_Set_State(unsigned char d)
 \r
 unsigned char ProgIO_Set_Get_State(unsigned char d)\r
 {\r
-  ProgIO_Set_State(d);\r
-\r
-  /* Read state of input pins:\r
+  /* Set state of output pins (s.a.)\r
+   * then read state of input pins:\r
    *\r
    * TDO => d.0\r
    * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)\r
    */\r
 \r
+  ProgIO_Set_State(d);\r
    return (GetASDO()<<1)|GetTDO();\r
 }\r
 \r