X-Git-Url: http://git.rot13.org/?p=fx2fw-sdcc;a=blobdiff_plain;f=fx2%2Fsyncdelay.h;fp=fx2%2Fsyncdelay.h;h=3293fd922f2254151071de2fe796dca95d200514;hp=178f316eb5d75249d09d1939e1f5f20b8e7e1dfd;hb=bfdb50c8dfa96ad8a804b152c92c5a5880c8bdb7;hpb=750d9b37905b7a1cf9e8708c4688f3342c8be133

diff --git a/fx2/syncdelay.h b/fx2/syncdelay.h
index 178f316..3293fd9 100644
--- a/fx2/syncdelay.h
+++ b/fx2/syncdelay.h
@@ -1,128 +1,64 @@
 /* -*- c++ -*- */
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 /*-----------------------------------------------------------------------------
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  * Synchronization delay for FX2 access to specific registers
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  *-----------------------------------------------------------------------------
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  * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
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  * Copyright 2003 Free Software Foundation, Inc.
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  *-----------------------------------------------------------------------------
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  * This code is part of usbjtag. usbjtag is free software; you can redistribute
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  * it and/or modify it under the terms of the GNU General Public License as
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  * published by the Free Software Foundation; either version 2 of the License,
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  * or (at your option) any later version. usbjtag is distributed in the hope
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  * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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  * GNU General Public License for more details.  You should have received a
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  * copy of the GNU General Public License along with this program in the file
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  * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
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  * St, Fifth Floor, Boston, MA  02110-1301  USA
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  *-----------------------------------------------------------------------------
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  */
 
-
-
 #ifndef _SYNCDELAY_H_
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 #define _SYNCDELAY_H_
 
-
-
 /*
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  * Magic delay required between access to certain xdata registers (TRM page 15-106).
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  * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles.  Each
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  * NOP is a single cycle....
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  *
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  * From TRM page 15-105:
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  *
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  * Under certain conditions, some read and write access to the FX2 registers must
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  * be separated by a "synchronization delay".  The delay is necessary only under the
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  * following conditions:
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  *
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  *   - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
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  *     of the registers listed below.
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  *
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  *   - between a write to one of the registers listed below and a read from any register
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  *     in the 0xE600 - 0xE6FF range.
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  *
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  *   Registers which require a synchronization delay:
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  *
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  *	FIFORESET			FIFOPINPOLAR
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  *	INPKTEND			EPxBCH:L
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  *	EPxFIFOPFH:L			EPxAUTOINLENH:L
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  *	EPxFIFOCFG			EPxGPIFFLGSEL
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  *	PINFLAGSAB			PINFLAGSCD
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  *	EPxFIFOIE			EPxFIFOIRQ
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  *	GPIFIE				GPIFIRQ
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  *	UDMACRCH:L			GPIFADRH:L
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  *	GPIFTRIG			EPxGPIFTRIG
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  *	OUTPKTEND			REVCTL
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  *	GPIFTCB3			GPIFTCB2
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  *	GPIFTCB1			GPIFTCB0
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  */
 
-
-
 /*
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  * FIXME ensure that the peep hole optimizer isn't screwing us
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  */
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 #define	SYNCDELAY	_asm nop; nop; nop; _endasm
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 #define	NOP		_asm nop; _endasm
 
 
-
-
-
 #endif /* _SYNCDELAY_H_ */
-