git.rot13.org Git - goodfet/blob - client/ATMEL_USART.py

   1
   2 """
   3 This library helps interface with USARTs on Atmel microcontrollers.  The library has been modeled after the AT91X40 series (1354D-ATARM-08/02).  AT91SAM7 has also been thrown in a little.
   4 """
   5
   6 USART0_BASE = 0xfffd0000
   7 USART1_BASE = 0xfffcc000
   8
   9 US_CR_OFF =     0x00    # wO
  10 US_MR_OFF =     0x04    # R/w
  11 US_IER_OFF =    0x08    # wO
  12 US_IDR_OFF =    0x0c    # wO
  13
  14 US_IMR_OFF =    0x10    # RO
  15 US_CSR_OFF =    0x14    # RO
  16 US_RHR_OFF =    0x18    # RO
  17 US_THR_OFF =    0x1c    # wO
  18
  19 US_BRGR_OFF =   0x20    # R/w
  20 US_RTOR_OFF =   0x24    # R/w
  21 US_TTGR_OFF =   0x28    # R/w
  22
  23 US_RPR_OFF =    0x30    # R/w   - AT91X40
  24 US_RCR_OFF =    0x34    # R/w   - AT91X40
  25 US_TPR_OFF =    0x38    # R/w   - AT91X40
  26 US_TCR_OFF =    0x3c    # R/w   - AT91X40
  27
  28 US_FIDI_OFF =   0x40    # R/w   - AT91SAM7
  29 US_NER_OFF =    0x44    # RO    - AT91SAM7
  30 US_IF_OFF =     0x4c    # R/w   - AT91SAM7
  31
  32 CR_RSTRX =      1<<2
  33 CR_RSTTX =      1<<3
  34 CR_RXEN =       1<<4
  35 CR_RXDIS =      1<<5
  36 CR_TXEN =       1<<6
  37 CR_TXDIS =      1<<7
  38 CR_RSTSTA =     1<<8
  39 CR_STTBRK =     1<<9
  40 CR_STPBRK =     1<<10
  41 CR_STTTO =      1<<11
  42 CR_SENDA =      1<<12
  43 CR_RSTIT =      1<<13
  44 CR_RSTNACK =    1<<14
  45 CR_RETTO =      1<<15
  46 CR_DTREN =      1<<16
  47 CR_DTRDIS =     1<<17
  48 CR_RTSEN =      1<<18
  49 CR_RTSDIS =     1<<19
  50
  51 CSR_RXRDY =     1
  52 CSR_TXRDY =     1<<1
  53 CSR_RXBRK =     1<<2
  54 CSR_ENDRX =     1<<3
  55 CSR_ENDTX =     1<<4
  56 CSR_OVRE =      1<<5
  57 CSR_FRAME =     1<<6
  58 CSR_PARE =      1<<7
  59 CSR_TIMEOUT =   1<<8
  60 CSR_TXEMPTY =   1<<9
  61
  62 INTERRUPTS = {
  63         CSR_RXRDY:"RXRDY",
  64         CSR_TXRDY:"TXRDY",
  65         CSR_RXBRK:"RXBRK",
  66         CSR_ENDRX:"ENDRX",
  67         CSR_ENDTX:"ENDTX",
  68         CSR_OVRE:"OVRE",
  69         CSR_FRAME:"FRAME",
  70         CSR_PARE:"PARE",
  71         CSR_TIMEOUT:"TIMEOUT",
  72         CSR_TXEMPTY:"TXEMPTY",
  73         }
  74
  75 MR_USCLKS =     1<<4
  76 MR_CHRL =       1<<6
  77 MR_SYNC =       1<<8
  78 MR_PAR =        1<<9
  79 MR_NBSTOP =     1<<12
  80 MR_CHMOD =      1<<14
  81 MR_MODE9 =      1<<17
  82 MR_CLKO =       1<<18
  83
  84 MR_USCLK_INTERP = {
  85         0:"MCK",
  86         1:"MCK/8",
  87         2:"External (SCK)",
  88         3:"External (SCK)",
  89         }
  90
  91 class USART:
  92     def __init__(self, arm7_gf_client, base_addr=USART0_BASE):
  93         self.client = arm7_gf_client
  94         self.base_addr = base_addr
  95
  96     def setControlReg(self, cr):
  97         """ only integers, please """
  98         self.client.writeMem(self.base + US_CR_OFF, [cr])
  99     def getModeReg(self):
 100         return self.client.readMem(self.base + US_MR_OFF, 1)
 101     def setModeReg(self, mr):
 102         return self.client.writeMem(self.base + US_MR_OFF, [mr])
 103     def interruptEnable(self, mask=0):
 104         self.client.writeMem(self.base + US_IER_OFF, [mask])
 105     def interruptDisable(self, mask=0):
 106         self.client.writeMem(self.base + US_IDR_OFF, [mask])
 107
 108     def getInterruptMask(self):
 109         return self.client.readMem(self.base + US_IMR_OFF,1)
 110     def getChannelStatus(self):
 111         return self.client.readMem(self.base + US_CSR_OFF,1)
 112     def getRecvHoldReg(self):
 113         return self.client.readMem(self.base + US_RHR_OFF,1)
 114     def setXmitHoldReg(self, char):
 115         num, = struct.unpack("B",char)
 116         self.client.writeMem(self.base + US_THR_OFF,[num])
 117
 118     def getBaudRateGenReg(self):
 119         return self.client.readMem(self.base + US_BRGR_OFF,1)
 120     def setBaudRateGenReg(self, brgr):
 121         self.client.writeMem(self.base + US_BRGR_OFF,[brgr])
 122     def getRecvTOReg(self):
 123         return self.client.readMem(self.base + US_RTOR_OFF,1)
 124     def setRecvTOReg(self, rtor):
 125         self.client.writeMem(self.base + US_RTOR_OFF,[rtor])
 126     def getXmitTOReg(self):
 127         return self.client.readMem(self.base + US_TTOR_OFF,1)
 128     def setXmitTOReg(self, ttor):
 129         self.client.writeMem(self.base + US_TTOR_OFF,[ttor])
 130
 131     def getRecvPtrReg(self):
 132         return self.client.readMem(self.base + US_RPR_OFF,1)
 133     def setRecvPtrReg(self, rpr):
 134         self.client.writeMem(self.base + US_RPR_OFF,[rpr])
 135     def getRecvCtrReg(self):
 136         return self.client.readMem(self.base + US_RCR_OFF,1)
 137     def setRecvCtrReg(self, cpr):
 138         self.client.writeMem(self.base + US_RCR_OFF,[rcr])
 139     def getXmitPtrReg(self):
 140         return self.client.readMem(self.base + US_TPR_OFF,1)
 141     def setXmitPtrReg(self, tpr):
 142         self.client.writeMem(self.base + US_TPR_OFF,[tpr])
 143     def getXmitCtrReg(self):
 144         return self.client.readMem(self.base + US_TCR_OFF,1)
 145     def setXmitCtrReg(self, cpr):
 146         self.client.writeMem(self.base + US_TCR_OFF,[tcr])
 147
 148     def crResetRecv(self):
 149         self.setControlReg(CR_RSTRX)
 150     def crResetXmit(self):
 151         self.setControlReg(CR_RSTTX)
 152     def crEnableRecv(self):
 153         self.setControlReg(CR_RXEN)
 154     def crDisableRecv(self):
 155         self.setControlReg(CR_RXDIS)
 156     def crEnableXmit(self):
 157         self.setControlReg(CR_TXEN)
 158     def crDisableXmit(self):
 159         self.setControlReg(CR_TXDIS)
 160     def crResetStatus(self):
 161         self.setControlReg(CR_RSTSTA)
 162     def crStartBreak(self):
 163         self.setControlReg(CR_STTBRK)
 164     def crStopBreak(self):
 165         self.setControlReg(CR_STPBRK)
 166     def crStartTimeout(self):
 167         self.setControlReg(CR_STTTO)
 168     def crSendAddress(self):
 169         self.setControlReg(CR_SENDA)
 170     def crSendBreak(self):
 171         timeout = 0x100
 172         while (timeout > 0 and self.getChannelStatus() & CSR_TXRDY):
 173             time.sleep(.1)
 174         self.crStartBreak()
 175         timeout = 0x100
 176         while (timeout > 0 and self.getChannelStatus() & CSR_TXRDY):
 177             time.sleep(.1)
 178         self.crStopBreak()
 179
 180     def mrGetModeParts(self):
 181         mode = self.getMode()
 182         usart_mode = mode & 0xf
 183         usclks =    ((mode>>4) & 3)
 184         chrl =      ((mode>>6) & 3) + 5
 185         sync =      ((mode>>8) & 1)
 186         par =       ((mode>>9) & 7)
 187         nbstop =    ((mode>>12)& 3)
 188         chmode =    ((mode>>14)& 3)
 189         mode9 =     ((mode>>17)& 1)
 190         cklo =      ((mode>>18)& 1)
 191         return (usclks,chrl,sync,par,nbstop,chmode,mode9,cklo)
 192     def mrReprUsartMode(self):
 193         return ("normal","rs485","hwhandshake","modem","iso7816/t=0",
 194                 "reserved","iso7816/t=1","reserved","irda","reserved",
 195                 "reserved","reserved","reserved","reserved","reserved",
 196                 "reserved","reserved",)[self.mrGetModeParts()[0]]
 197     def mrReprSelectedClock(self):
 198         return MR_USCLKS_INTERP[self.mrGetModeParts()[1]]
 199     def mrReprParity(self):
 200         return ("even","odd","forced-0","forced-1","None","None","Multidrop")[self.mrGetModeParts()[4]]
 201     def mrReprStopBits(self):
 202         return ("1","1.5","2","reserved")[self.mrGetModeParts()[5]]
 203     def mrReprChannelMode(self):
 204         return ("normal","auto-echo","local-loopback","remote-loopback")[self.mrGetModeParts()[5]]
 205
 206     def csrReprStatus(self):
 207         csr = self.getControlStatus()
 208         output = []
 209         for bit in xrange(10):
 210             b = 1<<bit
 211             if csr & b:
 212                 output.append(INTERRUPTS[b])
 213         return "\n".join(output)
 214
 215
 216