git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430.c

   1 /*! \file jtag430.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430 JTAG (16-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag.h"
   9
  10
  11 unsigned int jtag430mode=MSP430X2MODE;
  12
  13 //! Set a register.
  14 void jtag430_setr(u8 reg, u16 val){
  15   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  16   jtag_dr_shift16(0x3401);// release low byte
  17   jtag_ir_shift8(IR_DATA_16BIT);
  18
  19   //0x4030 is "MOV #foo, r0"
  20   //Right-most field is register, so 0x4035 loads r5
  21   jtag_dr_shift16(0x4030+reg);
  22   CLRTCLK;
  23   SETTCLK;
  24   jtag_dr_shift16(val);// Value for the register
  25   CLRTCLK;
  26   jtag_ir_shift8(IR_ADDR_CAPTURE);
  27   SETTCLK;
  28   CLRTCLK ;// Now reg is set to new value.
  29   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  30   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
  31 }
  32
  33 //! Set the program counter.
  34 void jtag430_setpc(unsigned int adr){
  35   jtag430_setr(0,adr);
  36 }
  37
  38 //! Halt the CPU
  39 void jtag430_haltcpu(){
  40   //jtag430_setinstrfetch();
  41
  42   jtag_ir_shift8(IR_DATA_16BIT);
  43   jtag_dr_shift16(0x3FFF);//JMP $+0
  44
  45   CLRTCLK;
  46   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  47   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
  48   SETTCLK;
  49 }
  50
  51 //! Release the CPU
  52 void jtag430_releasecpu(){
  53   CLRTCLK;
  54   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  55   jtag_dr_shift16(0x2401);
  56   jtag_ir_shift8(IR_ADDR_CAPTURE);
  57   SETTCLK;
  58 }
  59
  60 //! Read data from address
  61 unsigned int jtag430_readmem(unsigned int adr){
  62   unsigned int toret;
  63   jtag430_haltcpu();
  64
  65   CLRTCLK;
  66   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  67
  68   if(adr>0xFF)
  69     jtag_dr_shift16(0x2409);//word read
  70   else
  71     jtag_dr_shift16(0x2419);//byte read
  72   jtag_ir_shift8(IR_ADDR_16BIT);
  73   jtag_dr_shift16(adr);//address
  74   jtag_ir_shift8(IR_DATA_TO_ADDR);
  75   SETTCLK;
  76
  77   CLRTCLK;
  78   toret=jtag_dr_shift16(0x0000);//16 bit return
  79
  80   return toret;
  81 }
  82
  83 //! Write data to address.
  84 void jtag430_writemem(unsigned int adr, unsigned int data){
  85   CLRTCLK;
  86   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  87   if(adr>0xFF)
  88     jtag_dr_shift16(0x2408);//word write
  89   else
  90     jtag_dr_shift16(0x2418);//byte write
  91   jtag_ir_shift8(IR_ADDR_16BIT);
  92   jtag_dr_shift16(adr);
  93   jtag_ir_shift8(IR_DATA_TO_ADDR);
  94   jtag_dr_shift16(data);
  95   SETTCLK;
  96 }
  97
  98 //! Write data to flash memory.  Must be preconfigured.
  99 void jtag430_writeflashword(unsigned int adr, unsigned int data){
 100
 101   CLRTCLK;
 102   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 103   jtag_dr_shift16(0x2408);//word write
 104   jtag_ir_shift8(IR_ADDR_16BIT);
 105   jtag_dr_shift16(adr);
 106   jtag_ir_shift8(IR_DATA_TO_ADDR);
 107   jtag_dr_shift16(data);
 108   SETTCLK;
 109
 110   //Return to read mode.
 111   CLRTCLK;
 112   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 113   jtag_dr_shift16(0x2409);
 114
 115   /*
 116   jtag430_writemem(adr,data);
 117   CLRTCLK;
 118   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 119   jtag_dr_shift16(0x2409);
 120   */
 121
 122   //Pulse TCLK
 123   jtag430_tclk_flashpulses(35); //35 standard
 124 }
 125
 126 //! Configure flash, then write a word.
 127 void jtag430_writeflash(unsigned int adr, unsigned int data){
 128   jtag430_haltcpu();
 129
 130   //FCTL1=0xA540, enabling flash write
 131   jtag430_writemem(0x0128, 0xA540);
 132   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 133   jtag430_writemem(0x012A, 0xA540);
 134   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 135   jtag430_writemem(0x012C, 0xA500); //all but info flash.
 136
 137   //Write the word itself.
 138   jtag430_writeflashword(adr,data);
 139
 140   //FCTL1=0xA500, disabling flash write
 141   jtag430_writemem(0x0128, 0xA500);
 142
 143   //jtag430_releasecpu();
 144 }
 145
 146
 147
 148 //! Power-On Reset
 149 void jtag430_por(){
 150   unsigned int jtagid;
 151
 152   // Perform Reset
 153   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 154   jtag_dr_shift16(0x2C01); // apply
 155   jtag_dr_shift16(0x2401); // remove
 156   CLRTCLK;
 157   SETTCLK;
 158   CLRTCLK;
 159   SETTCLK;
 160   CLRTCLK;
 161   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
 162   SETTCLK;
 163
 164   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
 165 }
 166
 167
 168
 169 #define ERASE_GLOB 0xA50E
 170 #define ERASE_ALLMAIN 0xA50C
 171 #define ERASE_MASS 0xA506
 172 #define ERASE_MAIN 0xA504
 173 #define ERASE_SGMT 0xA502
 174
 175 //! Configure flash, then write a word.
 176 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
 177   jtag430_haltcpu();
 178
 179   //FCTL1= erase mode
 180   jtag430_writemem(0x0128, mode);
 181   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 182   jtag430_writemem(0x012A, 0xA540);
 183   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 184   jtag430_writemem(0x012C, 0xA500);
 185
 186   //Write the erase word.
 187   jtag430_writemem(adr, 0x55AA);
 188   //Return to read mode.
 189   CLRTCLK;
 190   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 191   jtag_dr_shift16(0x2409);
 192
 193   //Send the pulses.
 194   jtag430_tclk_flashpulses(count);
 195
 196   //FCTL1=0xA500, disabling flash write
 197   jtag430_writemem(0x0128, 0xA500);
 198
 199   //jtag430_releasecpu();
 200 }
 201
 202
 203 //! Reset the TAP state machine.
 204 void jtag430_resettap(){
 205   int i;
 206   // Settle output
 207   SETTDI; //430X2
 208   SETTMS;
 209   //SETTDI; //classic
 210   TCKTOCK;
 211
 212   // Navigate to reset state.
 213   // Should be at least six.
 214   for(i=0;i<4;i++){
 215     TCKTOCK;
 216   }
 217
 218   // test-logic-reset
 219   CLRTMS;
 220   TCKTOCK;
 221   SETTMS;
 222   // idle
 223
 224
 225   /* sacred, by spec.
 226      Sometimes this isn't necessary.  */
 227   // fuse check
 228   CLRTMS;
 229   delay(50);
 230   SETTMS;
 231   CLRTMS;
 232   delay(50);
 233   SETTMS;
 234   /**/
 235
 236 }
 237
 238 //! Start JTAG, take pins
 239 void jtag430_start(){
 240   jtagsetup();
 241
 242   //Known-good starting position.
 243   //Might be unnecessary.
 244   SETTST;
 245   SETRST;
 246   delay(0xFFFF);
 247
 248   #ifndef SBWREWRITE
 249   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 250   CLRRST;
 251   delay(100); //100
 252   CLRTST;
 253   delay(50);  //50
 254   SETTST;
 255   delay(50);  //50
 256   SETRST;
 257   P5DIR&=~RST;
 258   delay(0xFFFF);
 259   #endif
 260
 261   //Perform a reset and disable watchdog.
 262   jtag430_por();
 263   jtag430_writemem(0x120,0x5a80);//disable watchdog
 264
 265   jtag430_haltcpu();
 266 }
 267
 268 //! Start normally, not JTAG.
 269 void jtag430_stop(){
 270   debugstr("Exiting JTAG.");
 271   jtagsetup();
 272
 273   //Known-good starting position.
 274   //Might be unnecessary.
 275   //SETTST;
 276   CLRTST;
 277   SETRST;
 278   delay(0xFFFF);
 279
 280   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 281   CLRRST;
 282   delay(0xFFFF);
 283   SETRST;
 284   //P5DIR&=~RST;
 285   //delay(0xFFFF);
 286
 287 }
 288
 289 //! Set CPU to Instruction Fetch
 290 void jtag430_setinstrfetch(){
 291
 292   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 293
 294   // Wait until instruction fetch state.
 295   while(1){
 296     if (jtag_dr_shift16(0x0000) & 0x0080)
 297       return;
 298     CLRTCLK;
 299     SETTCLK;
 300   }
 301 }
 302
 303
 304 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
 305 void jtag430handle(unsigned char app,
 306                    unsigned char verb,
 307                    unsigned long len){
 308   unsigned long at;
 309   unsigned int i, val;
 310
 311   //debugstr("Classic MSP430 handler.");
 312
 313
 314   /* FIXME
 315    * Sometimes JTAG doesn't init correctly.
 316    * This restarts the connection if the masked-rom
 317    * chip ID cannot be read.  Should print warning
 318    * for testing server.
 319    */
 320   while((i=jtag430_readmem(0xff0))==0xFFFF){
 321     jtag430_start();
 322     P1OUT^=1;
 323   }
 324   P1OUT&=~1;
 325
 326   switch(verb){
 327   case START:
 328     //Enter JTAG mode.
 329     jtag430_start();
 330     //TAP setup, fuse check
 331     jtag430_resettap();
 332
 333     cmddata[0]=jtag_ir_shift8(IR_BYPASS);
 334     txdata(app,verb,1);
 335
 336     break;
 337   case STOP:
 338     jtag430_stop();
 339     txdata(app,verb,0);
 340     break;
 341   case JTAG430_HALTCPU:
 342     jtag430_haltcpu();
 343     txdata(app,verb,0);
 344     break;
 345   case JTAG430_RELEASECPU:
 346     jtag430_releasecpu();
 347     txdata(app,verb,0);
 348     break;
 349   case JTAG430_SETINSTRFETCH:
 350     jtag430_setinstrfetch();
 351     txdata(app,verb,0);
 352     break;
 353
 354   case JTAG430_READMEM:
 355   case PEEK:
 356     at=cmddatalong[0];
 357
 358     //Fetch large blocks for bulk fetches,
 359     //small blocks for individual peeks.
 360     if(len>5)
 361       len=(cmddataword[2]);//always even.
 362     else
 363       len=2;
 364     len&=~1;//clear lsbit
 365
 366     txhead(app,verb,len);
 367     for(i=0;i<len;i+=2){
 368       jtag430_resettap();
 369       val=jtag430_readmem(at);
 370
 371       at+=2;
 372       serial_tx(val&0xFF);
 373       serial_tx((val&0xFF00)>>8);
 374     }
 375     break;
 376   case JTAG430_WRITEMEM:
 377   case POKE:
 378     jtag430_haltcpu();
 379     jtag430_writemem(cmddataword[0],cmddataword[2]);
 380     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 381     txdata(app,verb,2);
 382     break;
 383     /*
 384   case JTAG430_WRITEFLASH:
 385
 386     //debugstr("Poking flash memory.");
 387     jtag430_writeflash(cmddataword[0],cmddataword[2]);
 388
 389     //Try again if failure.
 390     //if(cmddataword[2]!=jtag430_readmem(cmddataword[0]))
 391     //  jtag430_writeflash(cmddataword[0],cmddataword[2]);
 392
 393     //Return result.
 394     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 395
 396     txdata(app,verb,2);
 397     break; */
 398   case JTAG430_WRITEFLASH:
 399     at=cmddataword[0];
 400
 401     for(i=0;i<(len>>1)-2;i++){
 402       //debugstr("Poking flash memory.");
 403       jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 404       //Reflash if needed.  Try this twice to save grace?
 405       if(cmddataword[i]!=jtag430_readmem(at))
 406         jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 407     }
 408
 409     //Return result of first write as a word.
 410     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 411
 412     txdata(app,verb,2);
 413     break;
 414   case JTAG430_ERASEFLASH:
 415     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000);
 416     txdata(app,verb,0);
 417     break;
 418   case JTAG430_SETPC:
 419     jtag430_haltcpu();
 420     jtag430_setpc(cmddataword[0]);
 421     txdata(app,verb,0);
 422     break;
 423   case JTAG430_SETREG:
 424     jtag430_setr(cmddata[0],cmddataword[1]);
 425     txdata(app,verb,0);
 426     break;
 427   case JTAG430_GETREG:
 428     //jtag430_getr(cmddata[0]);
 429     debugstr("JTAG430_GETREG not yet implemented.");
 430     cmddataword[0]=0xDEAD;
 431     txdata(app,verb,2);
 432     break;
 433   case JTAG430_COREIP_ID:
 434   case JTAG430_DEVICE_ID:
 435     cmddataword[0]=0;
 436     cmddataword[1]=0;
 437     txdata(app,verb,4);
 438     break;
 439
 440   default:
 441     jtaghandle(app,verb,len);
 442   }
 443   //jtag430_resettap();  //DO NOT UNCOMMENT
 444 }