469e03c04fe77fb13a0661631f4c5eb99cf9f8cf
[goodfet] / firmware / apps / jtag / jtag430.c
1 /*! \file jtag430.c
2   \author Travis Goodspeed <travis at radiantmachines.com>
3   \brief MSP430 JTAG (16-bit)
4 */
5
6 #include "platform.h"
7 #include "command.h"
8 #include "jtag430.h"
9
10
11 unsigned int jtag430mode=MSP430X2MODE;
12
13 //! Set a register.
14 void jtag430_setr(u8 reg, u16 val){
15   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
16   jtag_dr_shift16(0x3401);// release low byte
17   jtag_ir_shift8(IR_DATA_16BIT);
18   
19   //0x4030 is "MOV #foo, r0"
20   //Right-most field is register, so 0x4035 loads r5
21   jtag_dr_shift16(0x4030+reg);
22   CLRTCLK;
23   SETTCLK;
24   jtag_dr_shift16(val);// Value for the register
25   CLRTCLK;
26   jtag_ir_shift8(IR_ADDR_CAPTURE);
27   SETTCLK;
28   CLRTCLK ;// Now reg is set to new value.
29   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
30   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
31 }
32
33 //! Set the program counter.
34 void jtag430_setpc(unsigned int adr){
35   jtag430_setr(0,adr);
36 }
37
38 //! Halt the CPU
39 void jtag430_haltcpu(){
40   //jtag430_setinstrfetch();
41   
42   jtag_ir_shift8(IR_DATA_16BIT);
43   jtag_dr_shift16(0x3FFF);//JMP $+0
44   
45   CLRTCLK;
46   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
47   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
48   SETTCLK;
49 }
50
51 //! Release the CPU
52 void jtag430_releasecpu(){
53   CLRTCLK;
54   //debugstr("Releasing target MSP430.");
55   
56   /*
57   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
58   jtag_dr_shift16(0x2C01); //Apply reset.
59   jtag_dr_shift16(0x2401); //Release reset.
60   */
61   jtag_ir_shift8(IR_CNTRL_SIG_RELEASE);
62   SETTCLK;
63 }
64
65 //! Read data from address
66 unsigned int jtag430_readmem(unsigned int adr){
67   unsigned int toret;
68   jtag430_haltcpu();
69   
70   CLRTCLK;
71   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
72   
73   if(adr>0xFF)
74     jtag_dr_shift16(0x2409);//word read
75   else
76     jtag_dr_shift16(0x2419);//byte read
77   jtag_ir_shift8(IR_ADDR_16BIT);
78   jtag_dr_shiftadr(adr);//address
79   jtag_ir_shift8(IR_DATA_TO_ADDR);
80   SETTCLK;
81
82   CLRTCLK;
83   toret=jtag_dr_shift16(0x0000);//16 bit return
84   
85   return toret;
86 }
87
88 //! Write data to address.
89 void jtag430_writemem(unsigned int adr, unsigned int data){
90   CLRTCLK;
91   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
92   if(adr>0xFF)
93     jtag_dr_shift16(0x2408);//word write
94   else
95     jtag_dr_shift16(0x2418);//byte write
96   jtag_ir_shift8(IR_ADDR_16BIT);
97   jtag_dr_shiftadr(adr);
98   jtag_ir_shift8(IR_DATA_TO_ADDR);
99   jtag_dr_shift16(data);
100   SETTCLK;
101 }
102
103 //! Write data to flash memory.  Must be preconfigured.
104 void jtag430_writeflashword(unsigned int adr, unsigned int data){
105   
106   CLRTCLK;
107   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
108   jtag_dr_shift16(0x2408);//word write
109   jtag_ir_shift8(IR_ADDR_16BIT);
110   jtag_dr_shiftadr(adr);
111   jtag_ir_shift8(IR_DATA_TO_ADDR);
112   jtag_dr_shift16(data);
113   SETTCLK;
114   
115   //Return to read mode.
116   CLRTCLK;
117   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
118   jtag_dr_shift16(0x2409);
119   
120   /*
121   jtag430_writemem(adr,data);
122   CLRTCLK;
123   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
124   jtag_dr_shift16(0x2409);
125   */
126   
127   //Pulse TCLK
128   jtag430_tclk_flashpulses(35); //35 standard
129 }
130
131 //! Configure flash, then write a word.
132 void jtag430_writeflash(unsigned int adr, unsigned int data){
133   jtag430_haltcpu();
134   
135   //FCTL1=0xA540, enabling flash write
136   jtag430_writemem(0x0128, 0xA540);
137   //FCTL2=0xA540, selecting MCLK as source, DIV=1
138   jtag430_writemem(0x012A, 0xA540);
139   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
140   jtag430_writemem(0x012C, 0xA500); //all but info flash.
141   //if(jtag430_readmem(0x012C));
142   
143   //Write the word itself.
144   jtag430_writeflashword(adr,data);
145   
146   //FCTL1=0xA500, disabling flash write
147   jtag430_writemem(0x0128, 0xA500);
148   
149   //jtag430_releasecpu();
150 }
151
152
153
154 //! Power-On Reset
155 void jtag430_por(){
156   unsigned int jtagid;
157
158   // Perform Reset
159   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
160   jtag_dr_shift16(0x2C01); // apply
161   jtag_dr_shift16(0x2401); // remove
162   CLRTCLK;
163   SETTCLK;
164   CLRTCLK;
165   SETTCLK;
166   CLRTCLK;
167   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
168   SETTCLK;
169   
170   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
171 }
172
173
174
175 #define ERASE_GLOB 0xA50E
176 #define ERASE_ALLMAIN 0xA50C
177 #define ERASE_MASS 0xA506
178 #define ERASE_MAIN 0xA504
179 #define ERASE_SGMT 0xA502
180
181 //! Configure flash, then write a word.
182 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
183                         unsigned int info){
184   jtag430_haltcpu();
185   
186   //FCTL1= erase mode
187   jtag430_writemem(0x0128, mode);
188   //FCTL2=0xA540, selecting MCLK as source, DIV=1
189   jtag430_writemem(0x012A, 0xA540);
190   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
191   if(info)
192     jtag430_writemem(0x012C, 0xA540);
193   else
194     jtag430_writemem(0x012C, 0xA500);
195   
196   //Write the erase word.
197   jtag430_writemem(adr, 0x55AA);
198   //Return to read mode.
199   CLRTCLK;
200   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
201   jtag_dr_shift16(0x2409);
202   
203   //Send the pulses.
204   jtag430_tclk_flashpulses(count);
205   
206   //FCTL1=0xA500, disabling flash write
207   jtag430_writemem(0x0128, 0xA500);
208   
209   //jtag430_releasecpu();
210 }
211
212
213 //! Reset the TAP state machine.
214 void jtag430_resettap(){
215   int i;
216   // Settle output
217   SETTDI; //430X2
218   SETTMS;
219   //SETTDI; //classic
220   TCKTOCK;
221
222   // Navigate to reset state.
223   // Should be at least six.
224   for(i=0;i<4;i++){
225     TCKTOCK;
226   }
227
228   // test-logic-reset
229   CLRTMS;
230   TCKTOCK;
231   SETTMS;
232   // idle
233
234     
235   /* sacred, by spec.
236      Sometimes this isn't necessary.  */
237   // fuse check
238   CLRTMS;
239   delay(50);
240   SETTMS;
241   CLRTMS;
242   delay(50);
243   SETTMS;
244   /**/
245   
246 }
247
248 //! Start JTAG, take pins
249 void jtag430_start(){
250   jtagsetup();
251   
252   //Known-good starting position.
253   //Might be unnecessary.
254   SETTST;
255   SETRST;
256   delay(0xFFFF);
257
258
259   #ifndef SBWREWRITE
260   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
261   CLRRST;
262   delay(100); //100
263   CLRTST;
264   delay(50);  //50
265   SETTST;
266   delay(50);  //50
267   SETRST;
268   P5DIR&=~RST;
269   delay(0xFFFF);
270   #endif
271   
272   //Perform a reset and disable watchdog.
273   jtag430_por();
274   jtag430_writemem(0x120,0x5a80);//disable watchdog
275   
276   jtag430_haltcpu();
277 }
278
279 //! Stop JTAG.
280 void jtag430_stop(){
281   debugstr("Exiting JTAG.");
282   jtagsetup();
283   
284   //Known-good starting position.
285   //Might be unnecessary.
286   //SETTST;
287   CLRTST;
288   SETRST;
289   delay(0xFFFF);
290   
291   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
292   CLRRST;
293   delay(0xFFFF);
294   SETRST;
295   //P5DIR&=~RST;
296   //delay(0xFFFF);
297   
298 }
299
300 //! Set CPU to Instruction Fetch
301 void jtag430_setinstrfetch(){
302   
303   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
304
305   // Wait until instruction fetch state.
306   while(1){
307     if (jtag_dr_shift16(0x0000) & 0x0080)
308       return;
309     CLRTCLK;
310     SETTCLK;
311   }
312 }
313
314
315 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
316 void jtag430handle(unsigned char app,
317                    unsigned char verb,
318                    unsigned long len){
319   unsigned long at;
320   unsigned int i, val;
321   
322   
323   /* FIXME
324    * Sometimes JTAG doesn't init correctly.
325    * This restarts the connection if the masked-rom
326    * chip ID cannot be read.  Should print warning
327    * for testing server.
328    */
329   while((i=jtag430_readmem(0xff0))==0xFFFF){
330     debugstr("Reconnecting to target MSP430.");
331     jtag430_start();
332     PLEDOUT^=PLEDPIN;
333   }
334   PLEDOUT&=~PLEDPIN;
335   
336   
337   switch(verb){
338   case START:
339     //Enter JTAG mode.
340     jtag430_start();
341     //TAP setup, fuse check
342     jtag430_resettap();
343     
344     cmddata[0]=jtag_ir_shift8(IR_BYPASS);    
345     txdata(app,verb,1);
346
347     break;
348   case STOP:
349     jtag430_stop();
350     txdata(app,verb,0);
351     break;
352   case JTAG430_HALTCPU:
353     jtag430_haltcpu();
354     txdata(app,verb,0);
355     break;
356   case JTAG430_RELEASECPU:
357     jtag430_releasecpu();
358     txdata(app,verb,0);
359     break;
360   case JTAG430_SETINSTRFETCH:
361     jtag430_setinstrfetch();
362     txdata(app,verb,0);
363     break;
364     
365   case JTAG430_READMEM:
366   case PEEK:
367     at=cmddatalong[0];
368     
369     //Fetch large blocks for bulk fetches,
370     //small blocks for individual peeks.
371     if(len>5)
372       len=(cmddataword[2]);//always even.
373     else
374       len=2;
375     len&=~1;//clear lsbit
376     
377     txhead(app,verb,len);
378     for(i=0;i<len;i+=2){
379       jtag430_resettap();
380       val=jtag430_readmem(at);
381       
382       at+=2;
383       serial_tx(val&0xFF);
384       serial_tx((val&0xFF00)>>8);
385     }
386     break;
387   case JTAG430_WRITEMEM:
388   case POKE:
389     jtag430_haltcpu();
390     jtag430_writemem(cmddataword[0],cmddataword[2]);
391     cmddataword[0]=jtag430_readmem(cmddataword[0]);
392     txdata(app,verb,2);
393     break;
394     /*
395   case JTAG430_WRITEFLASH:
396
397     //debugstr("Poking flash memory.");
398     jtag430_writeflash(cmddataword[0],cmddataword[2]);
399     
400     //Try again if failure.
401     //if(cmddataword[2]!=jtag430_readmem(cmddataword[0]))
402     //  jtag430_writeflash(cmddataword[0],cmddataword[2]);
403     
404     //Return result.
405     cmddataword[0]=jtag430_readmem(cmddataword[0]);
406     
407     txdata(app,verb,2);
408     break; */
409   case JTAG430_WRITEFLASH:
410     at=cmddataword[0];
411     
412     for(i=0;i<(len>>1)-2;i++){
413       //debugstr("Poking flash memory.");
414       jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
415       //Reflash if needed.  Try this twice to save grace?
416       if(cmddataword[i]!=jtag430_readmem(at))
417         jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
418     }
419     
420     //Return result of first write as a word.
421     cmddataword[0]=jtag430_readmem(cmddataword[0]);
422     
423     txdata(app,verb,2);
424     break;
425   case JTAG430_ERASEFLASH:
426     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0);
427     txdata(app,verb,0);
428     break;
429   case JTAG430_ERASEINFO:
430     jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1);
431     txdata(app,verb,0);
432     break;
433   case JTAG430_SETPC:
434     jtag430_haltcpu();
435     //debughex("Setting PC.");
436     //debughex(cmddataword[0]);
437     jtag430_setpc(cmddataword[0]);
438     jtag430_releasecpu();
439     txdata(app,verb,0);
440     break;
441   case JTAG430_SETREG:
442     jtag430_setr(cmddata[0],cmddataword[1]);
443     txdata(app,verb,0);
444     break;
445   case JTAG430_GETREG:
446     //jtag430_getr(cmddata[0]);
447     debugstr("JTAG430_GETREG not yet implemented.");
448     cmddataword[0]=0xDEAD;
449     txdata(app,verb,2);
450     break;
451   case JTAG430_COREIP_ID:
452   case JTAG430_DEVICE_ID:
453     cmddataword[0]=0;
454     cmddataword[1]=0;
455     txdata(app,verb,4);
456     break;
457     
458   default:
459     jtaghandle(app,verb,len);
460   }
461   //jtag430_resettap();  //DO NOT UNCOMMENT
462 }