git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430.c

   1 /*! \file jtag430.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430 JTAG (16-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag.h"
   9
  10
  11 unsigned int jtag430mode=MSP430X2MODE;
  12
  13 //! Set a register.
  14 void jtag430_setr(u8 reg, u16 val){
  15   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  16   jtag_dr_shift16(0x3401);// release low byte
  17   jtag_ir_shift8(IR_DATA_16BIT);
  18
  19   //0x4030 is "MOV #foo, r0"
  20   //Right-most field is register, so 0x4035 loads r5
  21   jtag_dr_shift16(0x4030+reg);
  22   CLRTCLK;
  23   SETTCLK;
  24   jtag_dr_shift16(val);// Value for the register
  25   CLRTCLK;
  26   jtag_ir_shift8(IR_ADDR_CAPTURE);
  27   SETTCLK;
  28   CLRTCLK ;// Now reg is set to new value.
  29   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  30   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
  31 }
  32
  33 //! Set the program counter.
  34 void jtag430_setpc(unsigned int adr){
  35   jtag430_setr(0,adr);
  36 }
  37
  38 //! Halt the CPU
  39 void jtag430_haltcpu(){
  40   //jtag430_setinstrfetch();
  41
  42   jtag_ir_shift8(IR_DATA_16BIT);
  43   jtag_dr_shift16(0x3FFF);//JMP $+0
  44
  45   CLRTCLK;
  46   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  47   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
  48   SETTCLK;
  49 }
  50
  51 //! Release the CPU
  52 void jtag430_releasecpu(){
  53   CLRTCLK;
  54   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  55   jtag_dr_shift16(0x2401);
  56   jtag_ir_shift8(IR_ADDR_CAPTURE);
  57   SETTCLK;
  58 }
  59
  60 //! Read data from address
  61 unsigned int jtag430_readmem(unsigned int adr){
  62   unsigned int toret;
  63   jtag430_haltcpu();
  64
  65   CLRTCLK;
  66   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  67
  68   if(adr>0xFF)
  69     jtag_dr_shift16(0x2409);//word read
  70   else
  71     jtag_dr_shift16(0x2419);//byte read
  72   jtag_ir_shift8(IR_ADDR_16BIT);
  73   jtag_dr_shiftadr(adr);//address
  74   jtag_ir_shift8(IR_DATA_TO_ADDR);
  75   SETTCLK;
  76
  77   CLRTCLK;
  78   toret=jtag_dr_shift16(0x0000);//16 bit return
  79
  80   return toret;
  81 }
  82
  83 //! Write data to address.
  84 void jtag430_writemem(unsigned int adr, unsigned int data){
  85   CLRTCLK;
  86   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  87   if(adr>0xFF)
  88     jtag_dr_shift16(0x2408);//word write
  89   else
  90     jtag_dr_shift16(0x2418);//byte write
  91   jtag_ir_shift8(IR_ADDR_16BIT);
  92   jtag_dr_shiftadr(adr);
  93   jtag_ir_shift8(IR_DATA_TO_ADDR);
  94   jtag_dr_shift16(data);
  95   SETTCLK;
  96 }
  97
  98 //! Write data to flash memory.  Must be preconfigured.
  99 void jtag430_writeflashword(unsigned int adr, unsigned int data){
 100
 101   CLRTCLK;
 102   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 103   jtag_dr_shift16(0x2408);//word write
 104   jtag_ir_shift8(IR_ADDR_16BIT);
 105   jtag_dr_shiftadr(adr);
 106   jtag_ir_shift8(IR_DATA_TO_ADDR);
 107   jtag_dr_shift16(data);
 108   SETTCLK;
 109
 110   //Return to read mode.
 111   CLRTCLK;
 112   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 113   jtag_dr_shift16(0x2409);
 114
 115   /*
 116   jtag430_writemem(adr,data);
 117   CLRTCLK;
 118   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 119   jtag_dr_shift16(0x2409);
 120   */
 121
 122   //Pulse TCLK
 123   jtag430_tclk_flashpulses(35); //35 standard
 124 }
 125
 126 //! Configure flash, then write a word.
 127 void jtag430_writeflash(unsigned int adr, unsigned int data){
 128   jtag430_haltcpu();
 129
 130   //FCTL1=0xA540, enabling flash write
 131   jtag430_writemem(0x0128, 0xA540);
 132   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 133   jtag430_writemem(0x012A, 0xA540);
 134   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 135   jtag430_writemem(0x012C, 0xA500); //all but info flash.
 136   //if(jtag430_readmem(0x012C));
 137
 138   //Write the word itself.
 139   jtag430_writeflashword(adr,data);
 140
 141   //FCTL1=0xA500, disabling flash write
 142   jtag430_writemem(0x0128, 0xA500);
 143
 144   //jtag430_releasecpu();
 145 }
 146
 147
 148
 149 //! Power-On Reset
 150 void jtag430_por(){
 151   unsigned int jtagid;
 152
 153   // Perform Reset
 154   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 155   jtag_dr_shift16(0x2C01); // apply
 156   jtag_dr_shift16(0x2401); // remove
 157   CLRTCLK;
 158   SETTCLK;
 159   CLRTCLK;
 160   SETTCLK;
 161   CLRTCLK;
 162   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
 163   SETTCLK;
 164
 165   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
 166 }
 167
 168
 169
 170 #define ERASE_GLOB 0xA50E
 171 #define ERASE_ALLMAIN 0xA50C
 172 #define ERASE_MASS 0xA506
 173 #define ERASE_MAIN 0xA504
 174 #define ERASE_SGMT 0xA502
 175
 176 //! Configure flash, then write a word.
 177 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
 178                         unsigned int info){
 179   jtag430_haltcpu();
 180
 181   //FCTL1= erase mode
 182   jtag430_writemem(0x0128, mode);
 183   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 184   jtag430_writemem(0x012A, 0xA540);
 185   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 186   if(info)
 187     jtag430_writemem(0x012C, 0xA540);
 188   else
 189     jtag430_writemem(0x012C, 0xA500);
 190
 191   //Write the erase word.
 192   jtag430_writemem(adr, 0x55AA);
 193   //Return to read mode.
 194   CLRTCLK;
 195   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 196   jtag_dr_shift16(0x2409);
 197
 198   //Send the pulses.
 199   jtag430_tclk_flashpulses(count);
 200
 201   //FCTL1=0xA500, disabling flash write
 202   jtag430_writemem(0x0128, 0xA500);
 203
 204   //jtag430_releasecpu();
 205 }
 206
 207
 208 //! Reset the TAP state machine.
 209 void jtag430_resettap(){
 210   int i;
 211   // Settle output
 212   SETTDI; //430X2
 213   SETTMS;
 214   //SETTDI; //classic
 215   TCKTOCK;
 216
 217   // Navigate to reset state.
 218   // Should be at least six.
 219   for(i=0;i<4;i++){
 220     TCKTOCK;
 221   }
 222
 223   // test-logic-reset
 224   CLRTMS;
 225   TCKTOCK;
 226   SETTMS;
 227   // idle
 228
 229
 230   /* sacred, by spec.
 231      Sometimes this isn't necessary.  */
 232   // fuse check
 233   CLRTMS;
 234   delay(50);
 235   SETTMS;
 236   CLRTMS;
 237   delay(50);
 238   SETTMS;
 239   /**/
 240
 241 }
 242
 243 //! Start JTAG, take pins
 244 void jtag430_start(){
 245   jtagsetup();
 246
 247   //Known-good starting position.
 248   //Might be unnecessary.
 249   SETTST;
 250   SETRST;
 251   delay(0xFFFF);
 252
 253
 254   #ifndef SBWREWRITE
 255   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 256   CLRRST;
 257   delay(100); //100
 258   CLRTST;
 259   delay(50);  //50
 260   SETTST;
 261   delay(50);  //50
 262   SETRST;
 263   P5DIR&=~RST;
 264   delay(0xFFFF);
 265   #endif
 266
 267   //Perform a reset and disable watchdog.
 268   jtag430_por();
 269   jtag430_writemem(0x120,0x5a80);//disable watchdog
 270
 271   jtag430_haltcpu();
 272 }
 273
 274 //! Stop JTAG.
 275 void jtag430_stop(){
 276   debugstr("Exiting JTAG.");
 277   jtagsetup();
 278
 279   //Known-good starting position.
 280   //Might be unnecessary.
 281   //SETTST;
 282   CLRTST;
 283   SETRST;
 284   delay(0xFFFF);
 285
 286   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 287   CLRRST;
 288   delay(0xFFFF);
 289   SETRST;
 290   //P5DIR&=~RST;
 291   //delay(0xFFFF);
 292
 293 }
 294
 295 //! Set CPU to Instruction Fetch
 296 void jtag430_setinstrfetch(){
 297
 298   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 299
 300   // Wait until instruction fetch state.
 301   while(1){
 302     if (jtag_dr_shift16(0x0000) & 0x0080)
 303       return;
 304     CLRTCLK;
 305     SETTCLK;
 306   }
 307 }
 308
 309
 310 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
 311 void jtag430handle(unsigned char app,
 312                    unsigned char verb,
 313                    unsigned long len){
 314   unsigned long at;
 315   unsigned int i, val;
 316
 317   //debugstr("Classic MSP430 handler.");
 318
 319
 320   /* FIXME
 321    * Sometimes JTAG doesn't init correctly.
 322    * This restarts the connection if the masked-rom
 323    * chip ID cannot be read.  Should print warning
 324    * for testing server.
 325    */
 326   while((i=jtag430_readmem(0xff0))==0xFFFF){
 327     jtag430_start();
 328     P1OUT^=1;
 329   }
 330   P1OUT&=~1;
 331
 332
 333   switch(verb){
 334   case START:
 335     //Enter JTAG mode.
 336     jtag430_start();
 337     //TAP setup, fuse check
 338     jtag430_resettap();
 339
 340     cmddata[0]=jtag_ir_shift8(IR_BYPASS);
 341     txdata(app,verb,1);
 342
 343     break;
 344   case STOP:
 345     jtag430_stop();
 346     txdata(app,verb,0);
 347     break;
 348   case JTAG430_HALTCPU:
 349     jtag430_haltcpu();
 350     txdata(app,verb,0);
 351     break;
 352   case JTAG430_RELEASECPU:
 353     jtag430_releasecpu();
 354     txdata(app,verb,0);
 355     break;
 356   case JTAG430_SETINSTRFETCH:
 357     jtag430_setinstrfetch();
 358     txdata(app,verb,0);
 359     break;
 360
 361   case JTAG430_READMEM:
 362   case PEEK:
 363     at=cmddatalong[0];
 364
 365     //Fetch large blocks for bulk fetches,
 366     //small blocks for individual peeks.
 367     if(len>5)
 368       len=(cmddataword[2]);//always even.
 369     else
 370       len=2;
 371     len&=~1;//clear lsbit
 372
 373     txhead(app,verb,len);
 374     for(i=0;i<len;i+=2){
 375       jtag430_resettap();
 376       val=jtag430_readmem(at);
 377
 378       at+=2;
 379       serial_tx(val&0xFF);
 380       serial_tx((val&0xFF00)>>8);
 381     }
 382     break;
 383   case JTAG430_WRITEMEM:
 384   case POKE:
 385     jtag430_haltcpu();
 386     jtag430_writemem(cmddataword[0],cmddataword[2]);
 387     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 388     txdata(app,verb,2);
 389     break;
 390     /*
 391   case JTAG430_WRITEFLASH:
 392
 393     //debugstr("Poking flash memory.");
 394     jtag430_writeflash(cmddataword[0],cmddataword[2]);
 395
 396     //Try again if failure.
 397     //if(cmddataword[2]!=jtag430_readmem(cmddataword[0]))
 398     //  jtag430_writeflash(cmddataword[0],cmddataword[2]);
 399
 400     //Return result.
 401     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 402
 403     txdata(app,verb,2);
 404     break; */
 405   case JTAG430_WRITEFLASH:
 406     at=cmddataword[0];
 407
 408     for(i=0;i<(len>>1)-2;i++){
 409       //debugstr("Poking flash memory.");
 410       jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 411       //Reflash if needed.  Try this twice to save grace?
 412       if(cmddataword[i]!=jtag430_readmem(at))
 413         jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 414     }
 415
 416     //Return result of first write as a word.
 417     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 418
 419     txdata(app,verb,2);
 420     break;
 421   case JTAG430_ERASEFLASH:
 422     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0);
 423     txdata(app,verb,0);
 424     break;
 425   case JTAG430_ERASEINFO:
 426     jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1);
 427     txdata(app,verb,0);
 428     break;
 429   case JTAG430_SETPC:
 430     jtag430_haltcpu();
 431     jtag430_setpc(cmddataword[0]);
 432     txdata(app,verb,0);
 433     break;
 434   case JTAG430_SETREG:
 435     jtag430_setr(cmddata[0],cmddataword[1]);
 436     txdata(app,verb,0);
 437     break;
 438   case JTAG430_GETREG:
 439     //jtag430_getr(cmddata[0]);
 440     debugstr("JTAG430_GETREG not yet implemented.");
 441     cmddataword[0]=0xDEAD;
 442     txdata(app,verb,2);
 443     break;
 444   case JTAG430_COREIP_ID:
 445   case JTAG430_DEVICE_ID:
 446     cmddataword[0]=0;
 447     cmddataword[1]=0;
 448     txdata(app,verb,4);
 449     break;
 450
 451   default:
 452     jtaghandle(app,verb,len);
 453   }
 454   //jtag430_resettap();  //DO NOT UNCOMMENT
 455 }