2 \author Travis Goodspeed <travis at radiantmachines.com>
3 \brief MSP430 JTAG (16-bit)
11 unsigned int jtag430mode=MSP430X2MODE;
13 //! Set the program counter.
14 void jtag430_setpc(unsigned int adr){
15 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
16 jtag_dr_shift16(0x3401);// release low byte
17 jtag_ir_shift8(IR_DATA_16BIT);
18 jtag_dr_shift16(0x4030);//Instruction to load PC
21 jtag_dr_shift16(adr);// Value for PC
23 jtag_ir_shift8(IR_ADDR_CAPTURE);
25 CLRTCLK ;// Now PC is set to "PC_Value"
26 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
27 jtag_dr_shift16(0x2401);// low byte controlled by JTAG
31 void jtag430_haltcpu(){
32 //jtag430_setinstrfetch();
34 jtag_ir_shift8(IR_DATA_16BIT);
35 jtag_dr_shift16(0x3FFF);//JMP $+0
38 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
39 jtag_dr_shift16(0x2409);//set JTAG_HALT bit
44 void jtag430_releasecpu(){
46 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
47 jtag_dr_shift16(0x2401);
48 jtag_ir_shift8(IR_ADDR_CAPTURE);
52 //! Read data from address
53 unsigned int jtag430_readmem(unsigned int adr){
59 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
62 jtag_dr_shift16(0x2409);//word read
64 jtag_dr_shift16(0x2419);//byte read
65 jtag_ir_shift8(IR_ADDR_16BIT);
66 jtag_dr_shift16(adr);//address
67 jtag_ir_shift8(IR_DATA_TO_ADDR);
71 toret=jtag_dr_shift16(0x0000);//16 bit return
76 //! Write data to address.
77 void jtag430_writemem(unsigned int adr, unsigned int data){
79 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
81 jtag_dr_shift16(0x2408);//word write
83 jtag_dr_shift16(0x2418);//byte write
84 jtag_ir_shift8(IR_ADDR_16BIT);
86 jtag_ir_shift8(IR_DATA_TO_ADDR);
87 jtag_dr_shift16(data);
91 //! Write data to flash memory. Must be preconfigured.
92 void jtag430_writeflashword(unsigned int adr, unsigned int data){
95 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
96 jtag_dr_shift16(0x2408);//word write
97 jtag_ir_shift8(IR_ADDR_16BIT);
99 jtag_ir_shift8(IR_DATA_TO_ADDR);
100 jtag_dr_shift16(data);
103 //Return to read mode.
105 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
106 jtag_dr_shift16(0x2409);
109 jtag430_writemem(adr,data);
111 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
112 jtag_dr_shift16(0x2409);
116 jtag430_tclk_flashpulses(35); //35 standard
120 //! Configure flash, then write a word.
121 void jtag430_writeflash(unsigned int adr, unsigned int data){
124 //FCTL1=0xA540, enabling flash write
125 jtag430_writemem(0x0128, 0xA540);
126 //FCTL2=0xA540, selecting MCLK as source, DIV=1
127 jtag430_writemem(0x012A, 0xA540);
128 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
129 jtag430_writemem(0x012C, 0xA500); //all but info flash.
131 //Write the word itself.
132 jtag430_writeflashword(adr,data);
134 //FCTL1=0xA500, disabling flash write
135 jtag430_writemem(0x0128, 0xA500);
137 //jtag430_releasecpu();
147 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
148 jtag_dr_shift16(0x2C01); // apply
149 jtag_dr_shift16(0x2401); // remove
155 jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
158 jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
163 #define ERASE_GLOB 0xA50E
164 #define ERASE_ALLMAIN 0xA50C
165 #define ERASE_MASS 0xA506
166 #define ERASE_MAIN 0xA504
167 #define ERASE_SGMT 0xA502
169 //! Configure flash, then write a word.
170 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
174 jtag430_writemem(0x0128, mode);
175 //FCTL2=0xA540, selecting MCLK as source, DIV=1
176 jtag430_writemem(0x012A, 0xA540);
177 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
178 jtag430_writemem(0x012C, 0xA500);
180 //Write the erase word.
181 jtag430_writemem(adr, 0x55AA);
182 //Return to read mode.
184 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
185 jtag_dr_shift16(0x2409);
188 jtag430_tclk_flashpulses(count);
190 //FCTL1=0xA500, disabling flash write
191 jtag430_writemem(0x0128, 0xA500);
193 //jtag430_releasecpu();
197 //! Reset the TAP state machine.
198 void jtag430_resettap(){
206 // Navigate to reset state.
207 // Should be at least six.
222 Sometimes this isn't necessary. */
234 //! Start JTAG, take pins
235 void jtag430_start(){
238 //Known-good starting position.
239 //Might be unnecessary.
244 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
255 //Perform a reset and disable watchdog.
257 jtag430_writemem(0x120,0x5a80);//disable watchdog
262 //! Set CPU to Instruction Fetch
263 void jtag430_setinstrfetch(){
265 jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
267 // Wait until instruction fetch state.
269 if (jtag_dr_shift16(0x0000) & 0x0080)
277 //! Handles classic MSP430 JTAG commands. Forwards others to JTAG.
278 void jtag430handle(unsigned char app,
281 register char blocks;
285 //debugstr("Classic MSP430 handler.");
291 //TAP setup, fuse check
296 case JTAG430_HALTCPU:
300 case JTAG430_RELEASECPU:
301 jtag430_releasecpu();
304 case JTAG430_SETINSTRFETCH:
305 jtag430_setinstrfetch();
309 case JTAG430_READMEM:
312 cmddataword[0]=jtag430_readmem(cmddataword[0]);
315 blocks=(len>4?cmddata[4]:1);
318 //Fetch large blocks for bulk fetches,
319 //small blocks for individual peeks.
332 val=jtag430_readmem(at);
336 serial_tx((val&0xFF00)>>8);
340 case JTAG430_WRITEMEM:
342 jtag430_writemem(cmddataword[0],cmddataword[2]);
343 cmddataword[0]=jtag430_readmem(cmddataword[0]);
346 case JTAG430_WRITEFLASH:
347 //debugstr("Poking flash memory.");
348 jtag430_writeflash(cmddataword[0],cmddataword[2]);
349 cmddataword[0]=jtag430_readmem(cmddataword[0]);
352 case JTAG430_ERASEFLASH:
353 jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
354 jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
355 jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
359 jtag430_setpc(cmddataword[0]);
363 case JTAG430_COREIP_ID:
364 case JTAG430_DEVICE_ID:
371 jtaghandle(app,verb,len);