git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430.c

   1 /*! \file jtag430.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430 JTAG (16-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag.h"
   9
  10
  11 unsigned int jtag430mode=MSP430X2MODE;
  12
  13 //! Set a register.
  14 void jtag430_setr(u8 reg, u16 val){
  15   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  16   jtag_dr_shift16(0x3401);// release low byte
  17   jtag_ir_shift8(IR_DATA_16BIT);
  18
  19   //0x4030 is "MOV #foo, r0"
  20   //Right-most field is register, so 0x4035 loads r5
  21   jtag_dr_shift16(0x4030+reg);
  22   CLRTCLK;
  23   SETTCLK;
  24   jtag_dr_shift16(val);// Value for the register
  25   CLRTCLK;
  26   jtag_ir_shift8(IR_ADDR_CAPTURE);
  27   SETTCLK;
  28   CLRTCLK ;// Now reg is set to new value.
  29   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  30   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
  31 }
  32
  33 //! Set the program counter.
  34 void jtag430_setpc(unsigned int adr){
  35   jtag430_setr(0,adr);
  36 }
  37
  38 //! Halt the CPU
  39 void jtag430_haltcpu(){
  40   //jtag430_setinstrfetch();
  41
  42   jtag_ir_shift8(IR_DATA_16BIT);
  43   jtag_dr_shift16(0x3FFF);//JMP $+0
  44
  45   CLRTCLK;
  46   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  47   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
  48   SETTCLK;
  49 }
  50
  51 //! Release the CPU
  52 void jtag430_releasecpu(){
  53   CLRTCLK;
  54   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  55   jtag_dr_shift16(0x2401);
  56   jtag_ir_shift8(IR_ADDR_CAPTURE);
  57   SETTCLK;
  58 }
  59
  60 //! Read data from address
  61 unsigned int jtag430_readmem(unsigned int adr){
  62   unsigned int toret;
  63   jtag430_haltcpu();
  64
  65   CLRTCLK;
  66   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  67
  68   if(adr>0xFF)
  69     jtag_dr_shift16(0x2409);//word read
  70   else
  71     jtag_dr_shift16(0x2419);//byte read
  72   jtag_ir_shift8(IR_ADDR_16BIT);
  73   jtag_dr_shiftadr(adr);//address
  74   jtag_ir_shift8(IR_DATA_TO_ADDR);
  75   SETTCLK;
  76
  77   CLRTCLK;
  78   toret=jtag_dr_shift16(0x0000);//16 bit return
  79
  80   return toret;
  81 }
  82
  83 //! Write data to address.
  84 void jtag430_writemem(unsigned int adr, unsigned int data){
  85   CLRTCLK;
  86   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  87   if(adr>0xFF)
  88     jtag_dr_shift16(0x2408);//word write
  89   else
  90     jtag_dr_shift16(0x2418);//byte write
  91   jtag_ir_shift8(IR_ADDR_16BIT);
  92   jtag_dr_shiftadr(adr);
  93   jtag_ir_shift8(IR_DATA_TO_ADDR);
  94   jtag_dr_shift16(data);
  95   SETTCLK;
  96 }
  97
  98 //! Write data to flash memory.  Must be preconfigured.
  99 void jtag430_writeflashword(unsigned int adr, unsigned int data){
 100
 101   CLRTCLK;
 102   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 103   jtag_dr_shift16(0x2408);//word write
 104   jtag_ir_shift8(IR_ADDR_16BIT);
 105   jtag_dr_shiftadr(adr);
 106   jtag_ir_shift8(IR_DATA_TO_ADDR);
 107   jtag_dr_shift16(data);
 108   SETTCLK;
 109
 110   //Return to read mode.
 111   CLRTCLK;
 112   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 113   jtag_dr_shift16(0x2409);
 114
 115   /*
 116   jtag430_writemem(adr,data);
 117   CLRTCLK;
 118   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 119   jtag_dr_shift16(0x2409);
 120   */
 121
 122   //Pulse TCLK
 123   jtag430_tclk_flashpulses(35); //35 standard
 124 }
 125
 126 //! Configure flash, then write a word.
 127 void jtag430_writeflash(unsigned int adr, unsigned int data){
 128   jtag430_haltcpu();
 129
 130   //FCTL1=0xA540, enabling flash write
 131   jtag430_writemem(0x0128, 0xA540);
 132   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 133   jtag430_writemem(0x012A, 0xA540);
 134   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 135   jtag430_writemem(0x012C, 0xA500); //all but info flash.
 136
 137   //Write the word itself.
 138   jtag430_writeflashword(adr,data);
 139
 140   //FCTL1=0xA500, disabling flash write
 141   jtag430_writemem(0x0128, 0xA500);
 142
 143   //jtag430_releasecpu();
 144 }
 145
 146
 147
 148 //! Power-On Reset
 149 void jtag430_por(){
 150   unsigned int jtagid;
 151
 152   // Perform Reset
 153   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 154   jtag_dr_shift16(0x2C01); // apply
 155   jtag_dr_shift16(0x2401); // remove
 156   CLRTCLK;
 157   SETTCLK;
 158   CLRTCLK;
 159   SETTCLK;
 160   CLRTCLK;
 161   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
 162   SETTCLK;
 163
 164   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
 165 }
 166
 167
 168
 169 #define ERASE_GLOB 0xA50E
 170 #define ERASE_ALLMAIN 0xA50C
 171 #define ERASE_MASS 0xA506
 172 #define ERASE_MAIN 0xA504
 173 #define ERASE_SGMT 0xA502
 174
 175 //! Configure flash, then write a word.
 176 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
 177                         unsigned int info){
 178   jtag430_haltcpu();
 179
 180   //FCTL1= erase mode
 181   jtag430_writemem(0x0128, mode);
 182   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 183   jtag430_writemem(0x012A, 0xA540);
 184   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 185   if(info)
 186     jtag430_writemem(0x012C, 0xA540);
 187   else
 188     jtag430_writemem(0x012C, 0xA500);
 189
 190   //Write the erase word.
 191   jtag430_writemem(adr, 0x55AA);
 192   //Return to read mode.
 193   CLRTCLK;
 194   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 195   jtag_dr_shift16(0x2409);
 196
 197   //Send the pulses.
 198   jtag430_tclk_flashpulses(count);
 199
 200   //FCTL1=0xA500, disabling flash write
 201   jtag430_writemem(0x0128, 0xA500);
 202
 203   //jtag430_releasecpu();
 204 }
 205
 206
 207 //! Reset the TAP state machine.
 208 void jtag430_resettap(){
 209   int i;
 210   // Settle output
 211   SETTDI; //430X2
 212   SETTMS;
 213   //SETTDI; //classic
 214   TCKTOCK;
 215
 216   // Navigate to reset state.
 217   // Should be at least six.
 218   for(i=0;i<4;i++){
 219     TCKTOCK;
 220   }
 221
 222   // test-logic-reset
 223   CLRTMS;
 224   TCKTOCK;
 225   SETTMS;
 226   // idle
 227
 228
 229   /* sacred, by spec.
 230      Sometimes this isn't necessary.  */
 231   // fuse check
 232   CLRTMS;
 233   delay(50);
 234   SETTMS;
 235   CLRTMS;
 236   delay(50);
 237   SETTMS;
 238   /**/
 239
 240 }
 241
 242 //! Start JTAG, take pins
 243 void jtag430_start(){
 244   jtagsetup();
 245
 246   //Known-good starting position.
 247   //Might be unnecessary.
 248   SETTST;
 249   SETRST;
 250   delay(0xFFFF);
 251
 252
 253   #ifndef SBWREWRITE
 254   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 255   CLRRST;
 256   delay(100); //100
 257   CLRTST;
 258   delay(50);  //50
 259   SETTST;
 260   delay(50);  //50
 261   SETRST;
 262   P5DIR&=~RST;
 263   delay(0xFFFF);
 264   #endif
 265
 266   //Perform a reset and disable watchdog.
 267   jtag430_por();
 268   jtag430_writemem(0x120,0x5a80);//disable watchdog
 269
 270   jtag430_haltcpu();
 271 }
 272
 273 //! Stop JTAG.
 274 void jtag430_stop(){
 275   debugstr("Exiting JTAG.");
 276   jtagsetup();
 277
 278   //Known-good starting position.
 279   //Might be unnecessary.
 280   //SETTST;
 281   CLRTST;
 282   SETRST;
 283   delay(0xFFFF);
 284
 285   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 286   CLRRST;
 287   delay(0xFFFF);
 288   SETRST;
 289   //P5DIR&=~RST;
 290   //delay(0xFFFF);
 291
 292 }
 293
 294 //! Set CPU to Instruction Fetch
 295 void jtag430_setinstrfetch(){
 296
 297   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 298
 299   // Wait until instruction fetch state.
 300   while(1){
 301     if (jtag_dr_shift16(0x0000) & 0x0080)
 302       return;
 303     CLRTCLK;
 304     SETTCLK;
 305   }
 306 }
 307
 308
 309 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
 310 void jtag430handle(unsigned char app,
 311                    unsigned char verb,
 312                    unsigned long len){
 313   unsigned long at;
 314   unsigned int i, val;
 315
 316   //debugstr("Classic MSP430 handler.");
 317
 318
 319   /* FIXME
 320    * Sometimes JTAG doesn't init correctly.
 321    * This restarts the connection if the masked-rom
 322    * chip ID cannot be read.  Should print warning
 323    * for testing server.
 324    */
 325   while((i=jtag430_readmem(0xff0))==0xFFFF){
 326     jtag430_start();
 327     P1OUT^=1;
 328   }
 329   P1OUT&=~1;
 330
 331
 332   switch(verb){
 333   case START:
 334     //Enter JTAG mode.
 335     jtag430_start();
 336     //TAP setup, fuse check
 337     jtag430_resettap();
 338
 339     cmddata[0]=jtag_ir_shift8(IR_BYPASS);
 340     txdata(app,verb,1);
 341
 342     break;
 343   case STOP:
 344     jtag430_stop();
 345     txdata(app,verb,0);
 346     break;
 347   case JTAG430_HALTCPU:
 348     jtag430_haltcpu();
 349     txdata(app,verb,0);
 350     break;
 351   case JTAG430_RELEASECPU:
 352     jtag430_releasecpu();
 353     txdata(app,verb,0);
 354     break;
 355   case JTAG430_SETINSTRFETCH:
 356     jtag430_setinstrfetch();
 357     txdata(app,verb,0);
 358     break;
 359
 360   case JTAG430_READMEM:
 361   case PEEK:
 362     at=cmddatalong[0];
 363
 364     //Fetch large blocks for bulk fetches,
 365     //small blocks for individual peeks.
 366     if(len>5)
 367       len=(cmddataword[2]);//always even.
 368     else
 369       len=2;
 370     len&=~1;//clear lsbit
 371
 372     txhead(app,verb,len);
 373     for(i=0;i<len;i+=2){
 374       jtag430_resettap();
 375       val=jtag430_readmem(at);
 376
 377       at+=2;
 378       serial_tx(val&0xFF);
 379       serial_tx((val&0xFF00)>>8);
 380     }
 381     break;
 382   case JTAG430_WRITEMEM:
 383   case POKE:
 384     jtag430_haltcpu();
 385     jtag430_writemem(cmddataword[0],cmddataword[2]);
 386     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 387     txdata(app,verb,2);
 388     break;
 389     /*
 390   case JTAG430_WRITEFLASH:
 391
 392     //debugstr("Poking flash memory.");
 393     jtag430_writeflash(cmddataword[0],cmddataword[2]);
 394
 395     //Try again if failure.
 396     //if(cmddataword[2]!=jtag430_readmem(cmddataword[0]))
 397     //  jtag430_writeflash(cmddataword[0],cmddataword[2]);
 398
 399     //Return result.
 400     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 401
 402     txdata(app,verb,2);
 403     break; */
 404   case JTAG430_WRITEFLASH:
 405     at=cmddataword[0];
 406
 407     for(i=0;i<(len>>1)-2;i++){
 408       //debugstr("Poking flash memory.");
 409       jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 410       //Reflash if needed.  Try this twice to save grace?
 411       if(cmddataword[i]!=jtag430_readmem(at))
 412         jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 413     }
 414
 415     //Return result of first write as a word.
 416     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 417
 418     txdata(app,verb,2);
 419     break;
 420   case JTAG430_ERASEFLASH:
 421     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0);
 422     txdata(app,verb,0);
 423     break;
 424   case JTAG430_ERASEINFO:
 425     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,1);
 426     txdata(app,verb,0);
 427     break;
 428   case JTAG430_SETPC:
 429     jtag430_haltcpu();
 430     jtag430_setpc(cmddataword[0]);
 431     txdata(app,verb,0);
 432     break;
 433   case JTAG430_SETREG:
 434     jtag430_setr(cmddata[0],cmddataword[1]);
 435     txdata(app,verb,0);
 436     break;
 437   case JTAG430_GETREG:
 438     //jtag430_getr(cmddata[0]);
 439     debugstr("JTAG430_GETREG not yet implemented.");
 440     cmddataword[0]=0xDEAD;
 441     txdata(app,verb,2);
 442     break;
 443   case JTAG430_COREIP_ID:
 444   case JTAG430_DEVICE_ID:
 445     cmddataword[0]=0;
 446     cmddataword[1]=0;
 447     txdata(app,verb,4);
 448     break;
 449
 450   default:
 451     jtaghandle(app,verb,len);
 452   }
 453   //jtag430_resettap();  //DO NOT UNCOMMENT
 454 }