7 //! Set the program counter.
8 void jtag430_setpc(unsigned int adr){
9 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
10 jtag_dr_shift16(0x3401);// release low byte
11 jtag_ir_shift8(IR_DATA_16BIT);
12 jtag_dr_shift16(0x4030);//Instruction to load PC
15 jtag_dr_shift16(adr);// Value for PC
17 jtag_ir_shift8(IR_ADDR_CAPTURE);
19 CLRTCLK ;// Now PC is set to "PC_Value"
20 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
21 jtag_dr_shift16(0x2401);// low byte controlled by JTAG
25 void jtag430_haltcpu(){
26 //jtag430_setinstrfetch();
28 jtag_ir_shift8(IR_DATA_16BIT);
29 jtag_dr_shift16(0x3FFF);//JMP $+0
32 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
33 jtag_dr_shift16(0x2409);//set JTAG_HALT bit
38 void jtag430_releasecpu(){
40 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
41 jtag_dr_shift16(0x2401);
42 jtag_ir_shift8(IR_ADDR_CAPTURE);
46 //! Read data from address
47 unsigned int jtag430_readmem(unsigned int adr){
51 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
53 jtag_dr_shift16(0x2409);//word read
55 jtag_dr_shift16(0x2419);//byte read
56 jtag_ir_shift8(IR_ADDR_16BIT);
57 jtag_dr_shift16(adr);//address
58 jtag_ir_shift8(IR_DATA_TO_ADDR);
62 toret=jtag_dr_shift16(0x0000);//16 bit return
67 //! Write data to address.
68 void jtag430_writemem(unsigned int adr, unsigned int data){
70 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
72 jtag_dr_shift16(0x2408);//word write
74 jtag_dr_shift16(0x2418);//byte write
75 jtag_ir_shift8(IR_ADDR_16BIT);
77 jtag_ir_shift8(IR_DATA_TO_ADDR);
78 jtag_dr_shift16(data);
82 //! Defined in jtag430asm.S
83 void jtag430_tclk_flashpulses(int);
84 /* //! Pulse TCLK at 350kHz +/- 100kHz */
85 /* void jtag430_tclk_flashpulses(register i){ */
86 /* //TODO check this on a scope. */
89 /* //At 2MHz, 350kHz is obtained with 5 clocks of delay */
92 /* What happens if the frequency is too low or to high? */
93 /* Is there any risk of damaging the chip, or only of a poor write? */
104 //! Write data to flash memory. Must be preconfigured.
105 void jtag430_writeflashword(unsigned int adr, unsigned int data){
108 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
109 jtag_dr_shift16(0x2408);//word write
110 jtag_ir_shift8(IR_ADDR_16BIT);
111 jtag_dr_shift16(adr);
112 jtag_ir_shift8(IR_DATA_TO_ADDR);
113 jtag_dr_shift16(data);
116 //Return to read mode.
118 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
119 jtag_dr_shift16(0x2409);
122 jtag430_writemem(adr,data);
124 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
125 jtag_dr_shift16(0x2409);
128 jtag430_tclk_flashpulses(35); //35 standard
132 //! Configure flash, then write a word.
133 void jtag430_writeflash(unsigned int adr, unsigned int data){
136 //FCTL1=0xA540, enabling flash write
137 jtag430_writemem(0x0128, 0xA540);
138 //FCTL2=0xA540, selecting MCLK as source, DIV=1
139 jtag430_writemem(0x012A, 0xA540);
140 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
141 jtag430_writemem(0x012C, 0xA500);
143 //Write the word itself.
144 jtag430_writeflashword(adr,data);
146 //FCTL1=0xA500, disabling flash write
147 jtag430_writemem(0x0128, 0xA500);
149 jtag430_releasecpu();
157 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
158 jtag_dr_shift16(0x2C01); // apply
159 jtag_dr_shift16(0x2401); // remove
165 jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
168 jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
173 #define ERASE_GLOB 0xA50E
174 #define ERASE_ALLMAIN 0xA50C
175 #define ERASE_MASS 0xA506
176 #define ERASE_MAIN 0xA504
177 #define ERASE_SGMT 0xA502
179 //! Configure flash, then write a word.
180 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
184 jtag430_writemem(0x0128, mode);
185 //FCTL2=0xA540, selecting MCLK as source, DIV=1
186 jtag430_writemem(0x012A, 0xA540);
187 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
188 jtag430_writemem(0x012C, 0xA500);
190 //Write the erase word.
191 jtag430_writemem(adr, 0x55AA);
192 //Return to read mode.
194 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
195 jtag_dr_shift16(0x2409);
198 jtag430_tclk_flashpulses(count);
200 //FCTL1=0xA500, disabling flash write
201 jtag430_writemem(0x0128, 0xA500);
203 jtag430_releasecpu();
207 //! Reset the TAP state machine.
208 void jtag430_resettap(){
215 // Navigate to reset state.
216 // Should be at least six.
231 Sometimes this isn't necessary. */
243 //! Start JTAG, take pins
244 void jtag430_start(){
247 //Known-good starting position.
248 //Might be unnecessary.
253 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
264 //Perform a reset and disable watchdog.
268 //! Set CPU to Instruction Fetch
269 void jtag430_setinstrfetch(){
270 jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
272 // Wait until instruction fetch state.
274 if (jtag_dr_shift16(0x0000) & 0x0080)
281 //! Handles unique MSP430 JTAG commands. Forwards others to JTAG.
282 void jtag430handle(unsigned char app,
290 //TAP setup, fuse check
294 case JTAG430_HALTCPU:
298 case JTAG430_RELEASECPU:
299 jtag430_releasecpu();
302 case JTAG430_SETINSTRFETCH:
303 jtag430_setinstrfetch();
308 case JTAG430_READMEM:
310 cmddataword[0]=jtag430_readmem(cmddataword[0]);
313 case JTAG430_WRITEMEM:
315 jtag430_writemem(cmddataword[0],cmddataword[1]);
316 cmddataword[0]=jtag430_readmem(cmddataword[0]);
319 case JTAG430_WRITEFLASH:
320 jtag430_writeflash(cmddataword[0],cmddataword[1]);
321 cmddataword[0]=jtag430_readmem(cmddataword[0]);
324 case JTAG430_ERASEFLASH:
325 jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
326 jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
327 jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
331 jtag430_setpc(cmddataword[0]);
335 jtaghandle(app,verb,len);