git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430.c

   1 /*! \file jtag430.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430 JTAG (16-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag.h"
   9
  10
  11 unsigned int jtag430mode=MSP430X2MODE;
  12
  13 //! Set a register.
  14 void jtag430_setr(u8 reg, u16 val){
  15   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  16   jtag_dr_shift16(0x3401);// release low byte
  17   jtag_ir_shift8(IR_DATA_16BIT);
  18
  19   //0x4030 is "MOV #foo, r0"
  20   //Right-most field is register, so 0x4035 loads r5
  21   jtag_dr_shift16(0x4030+reg);
  22   CLRTCLK;
  23   SETTCLK;
  24   jtag_dr_shift16(val);// Value for the register
  25   CLRTCLK;
  26   jtag_ir_shift8(IR_ADDR_CAPTURE);
  27   SETTCLK;
  28   CLRTCLK ;// Now reg is set to new value.
  29   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  30   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
  31 }
  32
  33 //! Set the program counter.
  34 void jtag430_setpc(unsigned int adr){
  35   jtag430_setr(0,adr);
  36 }
  37
  38 //! Halt the CPU
  39 void jtag430_haltcpu(){
  40   //jtag430_setinstrfetch();
  41
  42   jtag_ir_shift8(IR_DATA_16BIT);
  43   jtag_dr_shift16(0x3FFF);//JMP $+0
  44
  45   CLRTCLK;
  46   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  47   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
  48   SETTCLK;
  49 }
  50
  51 //! Release the CPU
  52 void jtag430_releasecpu(){
  53   CLRTCLK;
  54   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  55   jtag_dr_shift16(0x2401);
  56   jtag_ir_shift8(IR_ADDR_CAPTURE);
  57   SETTCLK;
  58 }
  59
  60 //! Read data from address
  61 unsigned int jtag430_readmem(unsigned int adr){
  62   unsigned int toret;
  63   jtag430_haltcpu();
  64
  65   CLRTCLK;
  66   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  67
  68   if(adr>0xFF)
  69     jtag_dr_shift16(0x2409);//word read
  70   else
  71     jtag_dr_shift16(0x2419);//byte read
  72   jtag_ir_shift8(IR_ADDR_16BIT);
  73   jtag_dr_shift16(adr);//address
  74   jtag_ir_shift8(IR_DATA_TO_ADDR);
  75   SETTCLK;
  76
  77   CLRTCLK;
  78   toret=jtag_dr_shift16(0x0000);//16 bit return
  79
  80   return toret;
  81 }
  82
  83 //! Write data to address.
  84 void jtag430_writemem(unsigned int adr, unsigned int data){
  85   CLRTCLK;
  86   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  87   if(adr>0xFF)
  88     jtag_dr_shift16(0x2408);//word write
  89   else
  90     jtag_dr_shift16(0x2418);//byte write
  91   jtag_ir_shift8(IR_ADDR_16BIT);
  92   jtag_dr_shift16(adr);
  93   jtag_ir_shift8(IR_DATA_TO_ADDR);
  94   jtag_dr_shift16(data);
  95   SETTCLK;
  96 }
  97
  98 //! Write data to flash memory.  Must be preconfigured.
  99 void jtag430_writeflashword(unsigned int adr, unsigned int data){
 100
 101   CLRTCLK;
 102   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 103   jtag_dr_shift16(0x2408);//word write
 104   jtag_ir_shift8(IR_ADDR_16BIT);
 105   jtag_dr_shift16(adr);
 106   jtag_ir_shift8(IR_DATA_TO_ADDR);
 107   jtag_dr_shift16(data);
 108   SETTCLK;
 109
 110   //Return to read mode.
 111   CLRTCLK;
 112   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 113   jtag_dr_shift16(0x2409);
 114
 115   /*
 116   jtag430_writemem(adr,data);
 117   CLRTCLK;
 118   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 119   jtag_dr_shift16(0x2409);
 120   */
 121
 122   //Pulse TCLK
 123   jtag430_tclk_flashpulses(35); //35 standard
 124 }
 125
 126 //! Configure flash, then write a word.
 127 void jtag430_writeflash(unsigned int adr, unsigned int data){
 128   jtag430_haltcpu();
 129
 130   //FCTL1=0xA540, enabling flash write
 131   jtag430_writemem(0x0128, 0xA540);
 132   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 133   jtag430_writemem(0x012A, 0xA540);
 134   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 135   jtag430_writemem(0x012C, 0xA500); //all but info flash.
 136
 137   //Write the word itself.
 138   jtag430_writeflashword(adr,data);
 139
 140   //FCTL1=0xA500, disabling flash write
 141   jtag430_writemem(0x0128, 0xA500);
 142
 143   //jtag430_releasecpu();
 144 }
 145
 146
 147
 148 //! Power-On Reset
 149 void jtag430_por(){
 150   unsigned int jtagid;
 151
 152   // Perform Reset
 153   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 154   jtag_dr_shift16(0x2C01); // apply
 155   jtag_dr_shift16(0x2401); // remove
 156   CLRTCLK;
 157   SETTCLK;
 158   CLRTCLK;
 159   SETTCLK;
 160   CLRTCLK;
 161   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
 162   SETTCLK;
 163
 164   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
 165 }
 166
 167
 168
 169 #define ERASE_GLOB 0xA50E
 170 #define ERASE_ALLMAIN 0xA50C
 171 #define ERASE_MASS 0xA506
 172 #define ERASE_MAIN 0xA504
 173 #define ERASE_SGMT 0xA502
 174
 175 //! Configure flash, then write a word.
 176 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
 177   jtag430_haltcpu();
 178
 179   //FCTL1= erase mode
 180   jtag430_writemem(0x0128, mode);
 181   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 182   jtag430_writemem(0x012A, 0xA540);
 183   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 184   jtag430_writemem(0x012C, 0xA500);
 185
 186   //Write the erase word.
 187   jtag430_writemem(adr, 0x55AA);
 188   //Return to read mode.
 189   CLRTCLK;
 190   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 191   jtag_dr_shift16(0x2409);
 192
 193   //Send the pulses.
 194   jtag430_tclk_flashpulses(count);
 195
 196   //FCTL1=0xA500, disabling flash write
 197   jtag430_writemem(0x0128, 0xA500);
 198
 199   //jtag430_releasecpu();
 200 }
 201
 202
 203 //! Reset the TAP state machine.
 204 void jtag430_resettap(){
 205   int i;
 206   // Settle output
 207   SETTDI; //430X2
 208   SETTMS;
 209   //SETTDI; //classic
 210   TCKTOCK;
 211
 212   // Navigate to reset state.
 213   // Should be at least six.
 214   for(i=0;i<4;i++){
 215     TCKTOCK;
 216   }
 217
 218   // test-logic-reset
 219   CLRTMS;
 220   TCKTOCK;
 221   SETTMS;
 222   // idle
 223
 224
 225   /* sacred, by spec.
 226      Sometimes this isn't necessary.  */
 227   // fuse check
 228   CLRTMS;
 229   delay(50);
 230   SETTMS;
 231   CLRTMS;
 232   delay(50);
 233   SETTMS;
 234   /**/
 235
 236 }
 237
 238 //! Start JTAG, take pins
 239 void jtag430_start(){
 240   jtagsetup();
 241
 242   //Known-good starting position.
 243   //Might be unnecessary.
 244   SETTST;
 245   SETRST;
 246   delay(0xFFFF);
 247
 248
 249   #ifndef SBWREWRITE
 250   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 251   CLRRST;
 252   delay(100); //100
 253   CLRTST;
 254   delay(50);  //50
 255   SETTST;
 256   delay(50);  //50
 257   SETRST;
 258   P5DIR&=~RST;
 259   delay(0xFFFF);
 260   #endif
 261
 262   //Perform a reset and disable watchdog.
 263   jtag430_por();
 264   jtag430_writemem(0x120,0x5a80);//disable watchdog
 265
 266   jtag430_haltcpu();
 267 }
 268
 269 //! Stop JTAG.
 270 void jtag430_stop(){
 271   debugstr("Exiting JTAG.");
 272   jtagsetup();
 273
 274   //Known-good starting position.
 275   //Might be unnecessary.
 276   //SETTST;
 277   CLRTST;
 278   SETRST;
 279   delay(0xFFFF);
 280
 281   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 282   CLRRST;
 283   delay(0xFFFF);
 284   SETRST;
 285   //P5DIR&=~RST;
 286   //delay(0xFFFF);
 287
 288 }
 289
 290 //! Set CPU to Instruction Fetch
 291 void jtag430_setinstrfetch(){
 292
 293   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 294
 295   // Wait until instruction fetch state.
 296   while(1){
 297     if (jtag_dr_shift16(0x0000) & 0x0080)
 298       return;
 299     CLRTCLK;
 300     SETTCLK;
 301   }
 302 }
 303
 304
 305 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
 306 void jtag430handle(unsigned char app,
 307                    unsigned char verb,
 308                    unsigned long len){
 309   unsigned long at;
 310   unsigned int i, val;
 311
 312   //debugstr("Classic MSP430 handler.");
 313
 314
 315   /* FIXME
 316    * Sometimes JTAG doesn't init correctly.
 317    * This restarts the connection if the masked-rom
 318    * chip ID cannot be read.  Should print warning
 319    * for testing server.
 320    */
 321   while((i=jtag430_readmem(0xff0))==0xFFFF){
 322     jtag430_start();
 323     P1OUT^=1;
 324   }
 325   P1OUT&=~1;
 326
 327
 328   switch(verb){
 329   case START:
 330     //Enter JTAG mode.
 331     jtag430_start();
 332     //TAP setup, fuse check
 333     jtag430_resettap();
 334
 335     cmddata[0]=jtag_ir_shift8(IR_BYPASS);
 336     txdata(app,verb,1);
 337
 338     break;
 339   case STOP:
 340     jtag430_stop();
 341     txdata(app,verb,0);
 342     break;
 343   case JTAG430_HALTCPU:
 344     jtag430_haltcpu();
 345     txdata(app,verb,0);
 346     break;
 347   case JTAG430_RELEASECPU:
 348     jtag430_releasecpu();
 349     txdata(app,verb,0);
 350     break;
 351   case JTAG430_SETINSTRFETCH:
 352     jtag430_setinstrfetch();
 353     txdata(app,verb,0);
 354     break;
 355
 356   case JTAG430_READMEM:
 357   case PEEK:
 358     at=cmddatalong[0];
 359
 360     //Fetch large blocks for bulk fetches,
 361     //small blocks for individual peeks.
 362     if(len>5)
 363       len=(cmddataword[2]);//always even.
 364     else
 365       len=2;
 366     len&=~1;//clear lsbit
 367
 368     txhead(app,verb,len);
 369     for(i=0;i<len;i+=2){
 370       jtag430_resettap();
 371       val=jtag430_readmem(at);
 372
 373       at+=2;
 374       serial_tx(val&0xFF);
 375       serial_tx((val&0xFF00)>>8);
 376     }
 377     break;
 378   case JTAG430_WRITEMEM:
 379   case POKE:
 380     jtag430_haltcpu();
 381     jtag430_writemem(cmddataword[0],cmddataword[2]);
 382     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 383     txdata(app,verb,2);
 384     break;
 385     /*
 386   case JTAG430_WRITEFLASH:
 387
 388     //debugstr("Poking flash memory.");
 389     jtag430_writeflash(cmddataword[0],cmddataword[2]);
 390
 391     //Try again if failure.
 392     //if(cmddataword[2]!=jtag430_readmem(cmddataword[0]))
 393     //  jtag430_writeflash(cmddataword[0],cmddataword[2]);
 394
 395     //Return result.
 396     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 397
 398     txdata(app,verb,2);
 399     break; */
 400   case JTAG430_WRITEFLASH:
 401     at=cmddataword[0];
 402
 403     for(i=0;i<(len>>1)-2;i++){
 404       //debugstr("Poking flash memory.");
 405       jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 406       //Reflash if needed.  Try this twice to save grace?
 407       if(cmddataword[i]!=jtag430_readmem(at))
 408         jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 409     }
 410
 411     //Return result of first write as a word.
 412     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 413
 414     txdata(app,verb,2);
 415     break;
 416   case JTAG430_ERASEFLASH:
 417     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000);
 418     txdata(app,verb,0);
 419     break;
 420   case JTAG430_SETPC:
 421     jtag430_haltcpu();
 422     jtag430_setpc(cmddataword[0]);
 423     txdata(app,verb,0);
 424     break;
 425   case JTAG430_SETREG:
 426     jtag430_setr(cmddata[0],cmddataword[1]);
 427     txdata(app,verb,0);
 428     break;
 429   case JTAG430_GETREG:
 430     //jtag430_getr(cmddata[0]);
 431     debugstr("JTAG430_GETREG not yet implemented.");
 432     cmddataword[0]=0xDEAD;
 433     txdata(app,verb,2);
 434     break;
 435   case JTAG430_COREIP_ID:
 436   case JTAG430_DEVICE_ID:
 437     cmddataword[0]=0;
 438     cmddataword[1]=0;
 439     txdata(app,verb,4);
 440     break;
 441
 442   default:
 443     jtaghandle(app,verb,len);
 444   }
 445   //jtag430_resettap();  //DO NOT UNCOMMENT
 446 }