git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430asm.S

   1 .globl jtag430_tclk_flashpulses
   2 .type jtag430_tclk_flashpulses,@function //for linking
   3
   4 #define _GNU_ASSEMBLER_
   5 #include "config.h"
   6
   7 //This detects model, chooses appropriate timing.
   8 jtag430_tclk_flashpulses:
   9         mov &0x0ff0, r14
  10         cmp  #0x6cf1, r14       ;Is the chip an MSP430F1xx?
  11         jz jtag430_tclk_flashpulses_3mhz
  12         jmp jtag430_tclk_flashpulses_16mhz
  13
  14 // At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
  15 // At 16MHz, 33 to 62 cycles/loop are allowed.
  16 jtag430_tclk_flashpulses_3mhz:
  17         mov #P5OUT, r14
  18 pulseloop3:
  19         bis.b #2, @r14          ;SETTCLK, 3 cycles
  20         sub #1, r15             ; 1 cycle
  21         ;;  1+3+3+1+2=10, within limits
  22         nop
  23         nop
  24         nop                     ;10+3=13
  25
  26         bic.b #2, @r14          ;CLRTCLK, 3 cycles
  27         tst r15                 ; 1 cycle
  28         jnz pulseloop3          ; 2 cycles
  29         ret
  30
  31 jtag430_tclk_flashpulses_16mhz:
  32         mov #P5OUT, r14
  33 pulseloop16:
  34         bis.b #2, @r14          ;SETTCLK, 3 cycles
  35         sub #1, r15             ; 1 cycle
  36         ;;  1+3+3+1+2=10, beneath limits,
  37
  38         ;; +3+2=5, repeat 8 times to get 10+40=50, within limits
  39         push r11                ; 3 cycles
  40         pop r11                 ; 2 cycles
  41         push r11                ; 3 cycles
  42         pop r11                 ; 2 cycles
  43         push r11                ; 3 cycles
  44         pop r11                 ; 2 cycles
  45         push r11                ; 3 cycles
  46         pop r11                 ; 2 cycles
  47         push r11                ; 3 cycles
  48         pop r11                 ; 2 cycles
  49         push r11                ; 3 cycles
  50         pop r11                 ; 2 cycles
  51         push r11                ; 3 cycles
  52         pop r11                 ; 2 cycles
  53         push r11                ; 3 cycles
  54         pop r11                 ; 2 cycles
  55
  56
  57         bic.b #2, @r14          ;CLRTCLK, 3 cycles
  58         tst r15                 ; 1 cycle
  59         jnz pulseloop16         ; 2 cycles
  60         ret
  61