git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430asm.S

   1 .globl jtag430_tclk_flashpulses
   2 .type jtag430_tclk_flashpulses,@function //for linking
   3
   4 //This detects model, chooses appropriate timing.
   5 jtag430_tclk_flashpulses:
   6         mov &0x0ff0, r14
   7         cmp  #0x6cf1, r14       ;Is the chip an MSP430F1xx?
   8         jz jtag430_tclk_flashpulses_3mhz
   9         jmp jtag430_tclk_flashpulses_16mhz
  10
  11 // At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
  12 // At 16MHz, 33 to 62 cycles/loop are allowed.
  13 jtag430_tclk_flashpulses_3mhz:
  14         mov #0x0031, r14
  15 pulseloop3:
  16         bis.b #2, @r14          ;SETTCLK, 3 cycles
  17         sub #1, r15             ; 1 cycle
  18         ;;  1+3+3+1+2=10, within limits
  19         bic.b #2, @r14          ;CLRTCLK, 3 cycles
  20         tst r15                 ; 1 cycle
  21         jnz pulseloop3          ; 2 cycles
  22         ret
  23
  24 jtag430_tclk_flashpulses_16mhz:
  25         mov #0x0031, r14
  26 pulseloop16:
  27         bis.b #2, @r14          ;SETTCLK, 3 cycles
  28         sub #1, r15             ; 1 cycle
  29         ;;  1+3+3+1+2=10, beneath limits,
  30
  31         ;; +3+2=5, repeat 8 times to get 10+40=50, within limits
  32         push r11                ; 3 cycles
  33         pop r11                 ; 2 cycles
  34         push r11                ; 3 cycles
  35         pop r11                 ; 2 cycles
  36         push r11                ; 3 cycles
  37         pop r11                 ; 2 cycles
  38         push r11                ; 3 cycles
  39         pop r11                 ; 2 cycles
  40         push r11                ; 3 cycles
  41         pop r11                 ; 2 cycles
  42         push r11                ; 3 cycles
  43         pop r11                 ; 2 cycles
  44         push r11                ; 3 cycles
  45         pop r11                 ; 2 cycles
  46         push r11                ; 3 cycles
  47         pop r11                 ; 2 cycles
  48
  49
  50         bic.b #2, @r14          ;CLRTCLK, 3 cycles
  51         tst r15                 ; 1 cycle
  52         jnz pulseloop16         ; 2 cycles
  53         ret
  54