git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430asm.S

   1 .globl jtag430_tclk_flashpulses
   2 .type jtag430_tclk_flashpulses,@function //for linking
   3
   4 #define _GNU_ASSEMBLER_
   5 #include "config.h"
   6
   7 //We need to include port definitions,
   8 //but msp430.h is no long asm clean.
   9 #include <msp430f1612.h>
  10
  11 //This detects model, chooses appropriate timing.
  12 jtag430_tclk_flashpulses:
  13         mov &0x0ff0, r14
  14         cmp  #0x6cf1, r14       ;Is the chip an MSP430F1xx?
  15         jz jtag430_tclk_flashpulses_3mhz
  16         jmp jtag430_tclk_flashpulses_16mhz
  17
  18 // At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
  19 // At 16MHz, 33 to 62 cycles/loop are allowed.
  20 jtag430_tclk_flashpulses_3mhz:
  21         mov #P5OUT, r14
  22 pulseloop3:
  23         bis.b #2, @r14          ;SETTCLK, 3 cycles
  24         sub #1, r15             ; 1 cycle
  25         ;;  1+3+3+1+2=10, within limits
  26         nop
  27         nop
  28         nop                     ;10+3=13
  29
  30         bic.b #2, @r14          ;CLRTCLK, 3 cycles
  31         tst r15                 ; 1 cycle
  32         jnz pulseloop3          ; 2 cycles
  33         ret
  34
  35 jtag430_tclk_flashpulses_16mhz:
  36         mov #P5OUT, r14
  37 pulseloop16:
  38         bis.b #2, @r14          ;SETTCLK, 3 cycles
  39         sub #1, r15             ; 1 cycle
  40         ;;  1+3+3+1+2=10, beneath limits,
  41
  42         ;; +3+2=5, repeat 8 times to get 10+40=50, within limits
  43         push r11                ; 3 cycles
  44         pop r11                 ; 2 cycles
  45         push r11                ; 3 cycles
  46         pop r11                 ; 2 cycles
  47         push r11                ; 3 cycles
  48         pop r11                 ; 2 cycles
  49         push r11                ; 3 cycles
  50         pop r11                 ; 2 cycles
  51         push r11                ; 3 cycles
  52         pop r11                 ; 2 cycles
  53         push r11                ; 3 cycles
  54         pop r11                 ; 2 cycles
  55         push r11                ; 3 cycles
  56         pop r11                 ; 2 cycles
  57         push r11                ; 3 cycles
  58         pop r11                 ; 2 cycles
  59
  60
  61         bic.b #2, @r14          ;CLRTCLK, 3 cycles
  62         tst r15                 ; 1 cycle
  63         jnz pulseloop16         ; 2 cycles
  64         ret
  65