1 .globl jtag430_tclk_flashpulses
2 .type jtag430_tclk_flashpulses,@function //for linking
4 #define _GNU_ASSEMBLER_
7 //We need to include port definitions,
8 //but msp430.h is no long asm clean.
9 #include <msp430f1612.h>
11 //This detects model, chooses appropriate timing.
12 jtag430_tclk_flashpulses:
14 cmp #0x6cf1, r14 ;Is the chip an MSP430F1xx?
15 jz jtag430_tclk_flashpulses_3mhz
16 jmp jtag430_tclk_flashpulses_16mhz
18 // At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
19 // At 16MHz, 33 to 62 cycles/loop are allowed.
20 jtag430_tclk_flashpulses_3mhz:
23 bis.b #2, @r14 ;SETTCLK, 3 cycles
25 ;; 1+3+3+1+2=10, within limits
30 bic.b #2, @r14 ;CLRTCLK, 3 cycles
32 jnz pulseloop3 ; 2 cycles
35 jtag430_tclk_flashpulses_16mhz:
38 bis.b #2, @r14 ;SETTCLK, 3 cycles
40 ;; 1+3+3+1+2=10, beneath limits,
42 ;; +3+2=5, repeat 8 times to get 10+40=50, within limits
61 bic.b #2, @r14 ;CLRTCLK, 3 cycles
63 jnz pulseloop16 ; 2 cycles