Beginning support for the second UART.
[goodfet] / firmware / apps / jtag / jtag430asm.S
1 .globl jtag430_tclk_flashpulses
2 .type jtag430_tclk_flashpulses,@function //for linking
3
4
5 //! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
6 jtag430_tclk_flashpulses:
7         mov #0x0031, r14
8 pulseloop:      
9         bis.b #2, @r14          ;SETTCLK, 3 cycles
10         sub #1, r15             ; 1 cycle
11         ;;  1+3+3+1+2=10, within limits
12         bic.b #2, @r14          ;CLRTCLK, 3 cycles
13         tst r15                 ; 1 cycle
14         jnz pulseloop           ; 2 cycles
15         ret
16