git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430x2.c

   1 /*! \file jtag430x2.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430X2 JTAG (20-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag430.h"
   9
  10 unsigned char jtagid;
  11
  12 //! Get the JTAG ID
  13 unsigned char jtag430x2_jtagid(){
  14   jtag430_resettap();
  15   return jtagid=jtag_ir_shift8(IR_BYPASS);
  16 }
  17 //! Start JTAG, take pins
  18 unsigned char jtag430x2_start(){
  19   jtagsetup();
  20
  21   //Known-good starting position.
  22   //Might be unnecessary.
  23   SETTST;
  24   SETRST;
  25
  26   delay(0xFFFF);
  27
  28   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
  29   CLRRST;
  30   delay(20);//10
  31   CLRTST;
  32
  33   delay(10);//5
  34   SETTST;
  35   msdelay(10);//5
  36   SETRST;
  37   P5DIR&=~RST;
  38
  39   delay(0xFFFF);
  40
  41   //Perform a reset and disable watchdog.
  42   return jtag430x2_jtagid();
  43 }
  44
  45 //! Grab the core ID.
  46 unsigned int jtag430_coreid(){
  47   jtag_ir_shift8(IR_COREIP_ID);
  48   return jtag_dr_shift16(0);
  49 }
  50
  51 //! Grab the device ID.
  52 unsigned long jtag430_deviceid(){
  53   jtag_ir_shift8(IR_DEVICE_ID);
  54   return jtag_dr_shift20(0);
  55 }
  56
  57
  58 //! Write data to address
  59 void jtag430x2_writemem(unsigned long adr,
  60                         unsigned int data){
  61   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
  62   if(jtag_dr_shift16(0) & 0x0301){
  63     CLRTCLK;
  64     jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  65     if(adr>=0x100)
  66       jtag_dr_shift16(0x0500);//word mode
  67     else
  68       jtag_dr_shift16(0x0510);//byte mode
  69     jtag_ir_shift8(IR_ADDR_16BIT);
  70     jtag_dr_shift20(adr);
  71
  72     SETTCLK;
  73
  74     jtag_ir_shift8(IR_DATA_TO_ADDR);
  75     jtag_dr_shift16(data);//16 word
  76
  77     CLRTCLK;
  78     jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  79     jtag_dr_shift16(0x0501);
  80     SETTCLK;
  81
  82     CLRTCLK;
  83     SETTCLK;
  84     //init state
  85   }else{
  86     while(1) PLEDOUT^=PLEDPIN; //loop if locked up
  87   }
  88 }
  89
  90 //! Read data from address
  91 unsigned int jtag430x2_readmem(unsigned long adr){
  92   unsigned int toret=0;
  93   //unsigned int tries=5;
  94
  95   while(1){
  96     //do{
  97     jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
  98     //}while(!(jtag_dr_shift16(0) & 0x0301));
  99
 100     if(jtag_dr_shift16(0) & 0x0301){
 101       // Read Memory
 102       CLRTCLK;
 103       jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 104
 105       //if(adr>=0x100){
 106       jtag_dr_shift16(0x0501);//word read
 107       //}else{
 108       //jtag_dr_shift16(0x0511);//byte read
 109       //}
 110
 111       jtag_ir_shift8(IR_ADDR_16BIT);
 112       jtag_dr_shift20(adr); //20
 113
 114       jtag_ir_shift8(IR_DATA_TO_ADDR);
 115       SETTCLK;
 116       CLRTCLK;
 117       toret = jtag_dr_shift16(0x0000);
 118
 119       SETTCLK;
 120
 121       //Cycle a bit.
 122       CLRTCLK;
 123       SETTCLK;
 124       return toret;
 125     }
 126   }
 127   //return toret;
 128 }
 129
 130 //! Syncs a POR.
 131 unsigned int jtag430x2_syncpor(){
 132   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 133   jtag_dr_shift16(0x1501); //JTAG mode
 134   while(!(jtag_dr_shift16(0) & 0x200));
 135   return jtag430x2_por();
 136 }
 137
 138 //! Executes an MSP430X2 POR
 139 unsigned int jtag430x2_por(){
 140   unsigned int i = 0;
 141
 142   // tick
 143   CLRTCLK;
 144   SETTCLK;
 145
 146   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 147   jtag_dr_shift16(0x0C01);
 148   jtag_dr_shift16(0x0401);
 149
 150   //cycle
 151   for (i = 0; i < 10; i++){
 152     CLRTCLK;
 153     SETTCLK;
 154   }
 155
 156   jtag_dr_shift16(0x0501);
 157
 158   // tick
 159   CLRTCLK;
 160   SETTCLK;
 161
 162
 163   // Disable WDT
 164   jtag430x2_writemem(0x015C, 0x5A80);
 165
 166   // check state
 167   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 168   if(jtag_dr_shift16(0) & 0x0301)
 169     return(1);//ok
 170
 171   return 0;//error
 172 }
 173
 174
 175 //! Check the fuse.
 176 unsigned int jtag430x2_fusecheck(){
 177   int i;
 178   for(i=0;i<3;i++){
 179     jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 180     if(jtag_dr_shift16(0xAAAA)==0x5555)
 181       return 1;//blown
 182   }
 183   return 0;//unblown
 184 }
 185
 186
 187 //! Handles MSP430X2 JTAG commands.  Forwards others to JTAG.
 188 void jtag430x2handle(unsigned char app,
 189                      unsigned char verb,
 190                      unsigned long len){
 191   register char blocks;
 192
 193   unsigned int i,val;
 194   unsigned long at;
 195
 196   //jtag430_resettap();
 197
 198   if(verb!=START && jtag430mode==MSP430MODE){
 199     jtag430handle(app,verb,len);
 200     return;
 201   }
 202
 203   switch(verb){
 204   case START:
 205     //Enter JTAG mode.
 206     //do
 207     cmddata[0]=jtag430x2_start();
 208     //while(cmddata[0]==00 || cmddata[0]==0xFF);
 209
 210     //MSP430 or MSP430X
 211     if(jtagid==MSP430JTAGID){
 212       jtag430mode=MSP430MODE;
 213
 214       /* So the way this works is that a width of 20 does some
 215          backward-compatibility finagling, causing the correct value
 216          to be exchanged for addresses on 16-bit chips as well as the
 217          new MSP430X chips.  (This has only been verified on the
 218          MSP430F2xx family.  TODO verify for others.)
 219        */
 220
 221       drwidth=20;
 222
 223       //Perform a reset and disable watchdog.
 224       jtag430_por();
 225       jtag430_writemem(0x120,0x5a80);//disable watchdog
 226
 227       jtag430_haltcpu();
 228
 229       jtag430_resettap();
 230       txdata(app,verb,1);
 231       return;
 232     }else if(jtagid==MSP430X2JTAGID){
 233       jtag430mode=MSP430X2MODE;
 234       drwidth=20;
 235     }else{
 236       debugstr("JTAG version unknown.");
 237       txdata(app,NOK,1);
 238       return;
 239     }
 240
 241     jtag430x2_fusecheck();
 242
 243     jtag430x2_syncpor();
 244
 245     jtag430_resettap();
 246
 247     txdata(app,verb,1);
 248     break;
 249   case JTAG430_READMEM:
 250   case PEEK:
 251     blocks=(len>4?cmddata[4]:1);
 252     at=cmddatalong[0];
 253
 254     len=0x80;
 255     txhead(app,verb,len);
 256
 257     while(blocks--){
 258       for(i=0;i<len;i+=2){
 259         jtag430_resettap();
 260         delay(10);
 261
 262         val=jtag430x2_readmem(at);
 263
 264         at+=2;
 265         serial_tx(val&0xFF);
 266         serial_tx((val&0xFF00)>>8);
 267       }
 268     }
 269
 270     break;
 271   case JTAG430_COREIP_ID:
 272     cmddataword[0]=jtag430_coreid();
 273     txdata(app,verb,2);
 274     break;
 275   case JTAG430_DEVICE_ID:
 276     cmddatalong[0]=jtag430_deviceid();
 277     txdata(app,verb,4);
 278     break;
 279
 280   case JTAG430_WRITEMEM:
 281   case POKE:
 282     jtag430x2_writemem(cmddatalong[0],
 283                        cmddataword[2]);
 284     cmddataword[0]=jtag430x2_readmem(cmddatalong[0]);
 285     txdata(app,verb,2);
 286     break;
 287
 288     //unimplemented functions
 289   case JTAG430_HALTCPU:
 290   case JTAG430_RELEASECPU:
 291   case JTAG430_SETINSTRFETCH:
 292   case JTAG430_WRITEFLASH:
 293   case JTAG430_ERASEFLASH:
 294   case JTAG430_SETPC:
 295     txdata(app,NOK,0);
 296     break;
 297   default:
 298     jtaghandle(app,verb,len);
 299   }
 300   jtag430_resettap();
 301 }