git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430x2.c

   1 /*! \file jtag430x2.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430X2 JTAG (20-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag430.h"
   9
  10 unsigned char jtagid;
  11
  12 //! Get the JTAG ID
  13 unsigned char jtag430x2_jtagid(){
  14   jtag430_resettap();
  15   return jtagid=jtag_ir_shift8(IR_BYPASS);
  16 }
  17 //! Start JTAG, take pins
  18 unsigned char jtag430x2_start(){
  19   jtagsetup();
  20
  21   //Known-good starting position.
  22   //Might be unnecessary.
  23   SETTST;
  24   SETRST;
  25
  26   delay(0xFFFF);
  27
  28   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
  29   CLRRST;
  30   delay(20);//10
  31   CLRTST;
  32
  33   delay(10);//5
  34   SETTST;
  35   msdelay(10);//5
  36   SETRST;
  37   P5DIR&=~RST;
  38
  39   delay(0xFFFF);
  40
  41   //Perform a reset and disable watchdog.
  42   return jtag430x2_jtagid();
  43 }
  44
  45 //! Grab the core ID.
  46 unsigned int jtag430_coreid(){
  47   jtag_ir_shift8(IR_COREIP_ID);
  48   return jtag_dr_shift16(0);
  49 }
  50
  51 //! Grab the device ID.
  52 unsigned long jtag430_deviceid(){
  53   jtag_ir_shift8(IR_DEVICE_ID);
  54   return jtag_dr_shift20(0);
  55 }
  56
  57
  58 //! Write data to address
  59 void jtag430x2_writemem(unsigned long adr,
  60                         unsigned int data){
  61   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
  62   if(jtag_dr_shift16(0) & 0x0301){
  63     CLRTCLK;
  64     jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  65     if(adr>=0x100)
  66       jtag_dr_shift16(0x0500);//word mode
  67     else
  68       jtag_dr_shift16(0x0510);//byte mode
  69     jtag_ir_shift8(IR_ADDR_16BIT);
  70     jtag_dr_shift20(adr);
  71
  72     SETTCLK;
  73
  74     jtag_ir_shift8(IR_DATA_TO_ADDR);
  75     jtag_dr_shift16(data);//16 word
  76
  77     CLRTCLK;
  78     jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  79     jtag_dr_shift16(0x0501);
  80     SETTCLK;
  81
  82     CLRTCLK;
  83     SETTCLK;
  84     //init state
  85   }else{
  86     while(1) PLEDOUT^=PLEDPIN; //loop if locked up
  87   }
  88 }
  89
  90 //! Read data from address
  91 unsigned int jtag430x2_readmem(unsigned long adr){
  92   unsigned int toret=0;
  93   //unsigned int tries=5;
  94
  95   while(1){
  96     do{
  97       jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
  98     }while(!(jtag_dr_shift16(0) & 0x0301));
  99
 100     if(jtag_dr_shift16(0) & 0x0301){
 101       // Read Memory
 102       CLRTCLK;
 103       jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 104       if(adr>=0x100){
 105         jtag_dr_shift16(0x0501);//word read
 106       }else{
 107         jtag_dr_shift16(0x0511);//byte read
 108       }
 109
 110       jtag_ir_shift8(IR_ADDR_16BIT);
 111       jtag_dr_shift20(adr); //20
 112
 113       jtag_ir_shift8(IR_DATA_TO_ADDR);
 114       SETTCLK;
 115       CLRTCLK;
 116       toret = jtag_dr_shift16(0x0000);
 117
 118       SETTCLK;
 119
 120       //Cycle a bit.
 121       CLRTCLK;
 122       SETTCLK;
 123       return toret;
 124     }
 125   }
 126   //return toret;
 127 }
 128
 129 //! Syncs a POR.
 130 unsigned int jtag430x2_syncpor(){
 131   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 132   jtag_dr_shift16(0x1501); //JTAG mode
 133   while(!(jtag_dr_shift16(0) & 0x200));
 134   return jtag430x2_por();
 135 }
 136
 137 //! Executes an MSP430X2 POR
 138 unsigned int jtag430x2_por(){
 139   unsigned int i = 0;
 140
 141   // tick
 142   CLRTCLK;
 143   SETTCLK;
 144
 145   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 146   jtag_dr_shift16(0x0C01);
 147   jtag_dr_shift16(0x0401);
 148
 149   //cycle
 150   for (i = 0; i < 10; i++){
 151     CLRTCLK;
 152     SETTCLK;
 153   }
 154
 155   jtag_dr_shift16(0x0501);
 156
 157   // tick
 158   CLRTCLK;
 159   SETTCLK;
 160
 161
 162   // Disable WDT
 163   jtag430x2_writemem(0x015C, 0x5A80);
 164
 165   // check state
 166   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 167   if(jtag_dr_shift16(0) & 0x0301)
 168     return(1);//ok
 169
 170   return 0;//error
 171 }
 172
 173
 174 //! Check the fuse.
 175 unsigned int jtag430x2_fusecheck(){
 176   int i;
 177   for(i=0;i<3;i++){
 178     jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 179     if(jtag_dr_shift16(0xAAAA)==0x5555)
 180       return 1;//blown
 181   }
 182   return 0;//unblown
 183 }
 184
 185
 186 //! Handles MSP430X2 JTAG commands.  Forwards others to JTAG.
 187 void jtag430x2handle(unsigned char app,
 188                      unsigned char verb,
 189                      unsigned long len){
 190   register char blocks;
 191
 192   unsigned int i,val;
 193   unsigned long at;
 194
 195   //jtag430_resettap();
 196
 197   if(verb!=START && jtag430mode==MSP430MODE){
 198     jtag430handle(app,verb,len);
 199     return;
 200   }
 201
 202   switch(verb){
 203   case START:
 204     //Enter JTAG mode.
 205     //do
 206     cmddata[0]=jtag430x2_start();
 207     //while(cmddata[0]==00 || cmddata[0]==0xFF);
 208
 209     //MSP430 or MSP430X
 210     if(jtagid==MSP430JTAGID){
 211       jtag430mode=MSP430MODE;
 212
 213       /* So the way this works is that a width of 20 does some
 214          backward-compatibility finagling, causing the correct value
 215          to be exchanged for addresses on 16-bit chips as well as the
 216          new MSP430X chips.  (This has only been verified on the
 217          MSP430F2xx family.  TODO verify for others.)
 218        */
 219
 220       drwidth=20;
 221
 222       //Perform a reset and disable watchdog.
 223       jtag430_por();
 224       jtag430_writemem(0x120,0x5a80);//disable watchdog
 225
 226       jtag430_haltcpu();
 227
 228       jtag430_resettap();
 229       txdata(app,verb,1);
 230       return;
 231     }else if(jtagid==MSP430X2JTAGID){
 232       jtag430mode=MSP430X2MODE;
 233       drwidth=20;
 234     }else{
 235       debugstr("JTAG version unknown.");
 236       txdata(app,NOK,1);
 237       return;
 238     }
 239
 240     jtag430x2_fusecheck();
 241
 242     jtag430x2_syncpor();
 243
 244     jtag430_resettap();
 245
 246     txdata(app,verb,1);
 247     break;
 248   case JTAG430_READMEM:
 249   case PEEK:
 250     blocks=(len>4?cmddata[4]:1);
 251     at=cmddatalong[0];
 252
 253     len=0x80;
 254     txhead(app,verb,len);
 255
 256     while(blocks--){
 257       for(i=0;i<len;i+=2){
 258         jtag430_resettap();
 259         delay(10);
 260
 261         val=jtag430x2_readmem(at);
 262
 263         at+=2;
 264         serial_tx(val&0xFF);
 265         serial_tx((val&0xFF00)>>8);
 266       }
 267     }
 268
 269     break;
 270   case JTAG430_COREIP_ID:
 271     cmddataword[0]=jtag430_coreid();
 272     txdata(app,verb,2);
 273     break;
 274   case JTAG430_DEVICE_ID:
 275     cmddatalong[0]=jtag430_deviceid();
 276     txdata(app,verb,4);
 277     break;
 278
 279   case JTAG430_WRITEMEM:
 280   case POKE:
 281     jtag430x2_writemem(cmddatalong[0],
 282                        cmddataword[2]);
 283     cmddataword[0]=jtag430x2_readmem(cmddatalong[0]);
 284     txdata(app,verb,2);
 285     break;
 286
 287     //unimplemented functions
 288   case JTAG430_HALTCPU:
 289   case JTAG430_RELEASECPU:
 290   case JTAG430_SETINSTRFETCH:
 291   case JTAG430_WRITEFLASH:
 292   case JTAG430_ERASEFLASH:
 293   case JTAG430_SETPC:
 294     txdata(app,NOK,0);
 295     break;
 296   default:
 297     jtaghandle(app,verb,len);
 298   }
 299   jtag430_resettap();
 300 }