1 /*! \file jtagarm7tdmi.h
2 \brief JTAG handler functions for the ARM7TDMI family of processors
8 #define JTAGSTATE_ARM 0 // bit 4 on dbg status reg is low
9 #define JTAGSTATE_THUMB 1
11 unsigned char current_chain;
12 unsigned char current_dbgstate = -1;
13 //unsigned char last_halt_debug_state = -1;
14 //unsigned long last_halt_pc = -1;
20 void jtagarm7tdmi_start(void);
22 //! Set a 32-bit ARM register
23 void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
24 //! Get a 32-bit ARM register
25 unsigned long jtagarm7tdmi_get_register(unsigned long reg);
27 // ARM7TDMI-specific pins
28 // DBGRQ - GoodFET Pin 8
32 The instruction register is 4 bits in length.
33 There is no parity bit.
34 The fixed value 0001 is loaded into the instruction register during the CAPTURE-IR
36 The least significant bit of the instruction register is scanned in and scanned out first.
39 //4-bit ARM7TDMI JTAG commands, bit-swapped
40 #define ARM7TDMI_IR_EXTEST 0x0
41 #define ARM7TDMI_IR_SCAN_N 0x2
42 #define ARM7TDMI_IR_SAMPLE 0x3
43 #define ARM7TDMI_IR_RESTART 0x4
44 #define ARM7TDMI_IR_CLAMP 0x5
45 #define ARM7TDMI_IR_HIGHZ 0x7
46 #define ARM7TDMI_IR_CLAMPZ 0x9
47 #define ARM7TDMI_IR_INTEST 0xC
48 #define ARM7TDMI_IR_IDCODE 0xE
49 #define ARM7TDMI_IR_BYPASS 0xF
51 // read 3 bit - Debug Control
52 #define EICE_DBGCTRL 0
53 #define EICE_DBGCTRL_BITLEN 3
54 // read 5 bit - Debug Status
55 #define EICE_DBGSTATUS 1
56 #define EICE_DBGSTATUS_BITLEN 5
57 // read 6 bit - Debug Comms Control Register
59 #define EICE_DBGCCR_BITLEN 6
60 // r/w 32 bit - Debug Comms Data Register
62 // r/w 32 bit - Watchpoint 0 Address
63 #define EICE_WP0ADDR 8
64 // r/w 32 bit - Watchpoint 0 Addres Mask
65 #define EICE_WP0ADDRMASK 9
66 // r/w 32 bit - Watchpoint 0 Data
67 #define EICE_WP0DATA 10
68 // r/w 32 bit - Watchpoint 0 Data Masl
69 #define EICE_WP0DATAMASK 11
70 // r/w 9 bit - Watchpoint 0 Control Value
71 #define EICE_WP0CTRL 12
72 // r/w 8 bit - Watchpoint 0 Control Mask
73 #define EICE_WP0CTRLMASK 13
74 // r/w 32 bit - Watchpoint 0 Address
75 #define EICE_WP1ADDR 16
76 // r/w 32 bit - Watchpoint 0 Addres Mask
77 #define EICE_WP1ADDRMASK 17
78 // r/w 32 bit - Watchpoint 0 Data
79 #define EICE_WP1DATA 18
80 // r/w 32 bit - Watchpoint 0 Data Masl
81 #define EICE_WP1DATAMASK 19
82 // r/w 9 bit - Watchpoint 0 Control Value
83 #define EICE_WP1CTRL 20
84 // r/w 8 bit - Watchpoint 0 Control Mask
85 #define EICE_WP1CTRLMASK 21
88 //JTAGARM7TDMI commands
89 #define JTAGARM7_GET_REGISTER 0x87
90 #define JTAGARM7_SET_REGISTER 0x88
91 #define JTAGARM7_DEBUG_INSTR 0x89
92 // Really ARM specific stuff
93 #define JTAGARM7_SET_IR 0x90
94 #define JTAGARM7_WAIT_DBG 0x91
95 #define JTAGARM7_SHIFT_DR 0x92
96 #define JTAGARM7_CHAIN0 0x93
97 #define JTAGARM7_SCANCHAIN1 0x94
98 #define JTAGARM7_EICE_READ 0x95
99 #define JTAGARM7_EICE_WRITE 0x96
102 // for deeper understanding, read the instruction cycle timing section of:
103 // http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
104 #define EXECNOPARM 0xe1a00000L
105 #define ARM_INSTR_NOP 0xe1a00000L
106 #define ARM_INSTR_BX_R0 0xe12fff10L
107 #define ARM_INSTR_STR_Rx_r14 0xe58f0000L // from atmel docs
108 #define ARM_READ_REG ARM_INSTR_STR_Rx_r14
109 #define ARM_INSTR_LDR_Rx_r14 0xe5900000L // NOT from atmel docs (e59e0000L is from atmel docs)
110 #define ARM_WRITE_REG ARM_INSTR_LDR_Rx_r14
111 #define ARM_INSTR_LDR_R1_r0_4 0xe4901004L
112 #define ARM_READ_MEM ARM_INSTR_LDR_R1_r0_4
113 #define ARM_INSTR_STR_R1_r0_4 0xe4801004L
114 #define ARM_WRITE_MEM ARM_INSTR_STR_R1_r0_4
115 #define ARM_INSTR_MRS_R0_CPSR 0xe10f0000L
116 #define ARM_INSTR_MSR_cpsr_cxsf_R0 0xe12ff000L
117 #define ARM_INSTR_STMIA_R14_r0_rx 0xE88E0000L // add up to 65k to indicate which registers...
118 #define ARM_STORE_MULTIPLE ARM_INSTR_STMIA_R14_r0_rx
119 #define ARM_INSTR_SKANKREGS 0xE88F7fffL
120 #define ARM_INSTR_CLOBBEREGS 0xE89F7fffL
122 #define ARM_INSTR_B_IMM 0xea000000L
123 #define ARM_INSTR_BX_PC 0xe12fff10L // need to set r0 to the desired address
124 #define THUMB_INSTR_LDR_R0_r0 0x68006800L
125 #define THUMB_WRITE_REG THUMB_INSTR_LDR_R0_r0
126 #define THUMB_INSTR_STR_R0_r0 0x60006000L
127 #define THUMB_READ_REG THUMB_INSTR_STR_R0_r0
128 #define THUMB_INSTR_MOV_R0_PC 0x46b846b8L
129 #define THUMB_INSTR_MOV_PC_R0 0x46474647L
130 #define THUMB_INSTR_MOV_HiLo 0x46404640L
131 #define THUMB_INSTR_MOV_LoHi 0x46804680L
132 #define THUMB_INSTR_BX_PC 0x47784778L
133 #define THUMB_INSTR_NOP 0x1c001c00L
134 #define THUMB_SWAP_HiLo 0
135 #define THUMB_SWAP_LoHi 1
136 #define ARM_REG_PC 15
138 #define JTAG_ARM7TDMI_DBG_DBGACK 1
139 #define JTAG_ARM7TDMI_DBG_DBGRQ 2
140 #define JTAG_ARM7TDMI_DBG_IFEN 4
141 #define JTAG_ARM7TDMI_DBG_cgenL 8
142 #define JTAG_ARM7TDMI_DBG_TBIT 16