1 /*! \file jtagarm7tdmi.h
2 \brief JTAG handler functions for the ARM7TDMI family of processors
8 #define JTAGSTATE_ARM 0 // bit 4 on dbg status reg is low
9 #define JTAGSTATE_THUMB 1
11 unsigned long last_instr = -1;
12 unsigned char last_sysstate = 0;
13 unsigned char last_ir = -1;
14 unsigned char last_scanchain = -1;
15 unsigned char tapstate = 15;
16 unsigned char current_dbgstate = -1;
17 //unsigned char last_halt_debug_state = -1;
18 //unsigned long last_halt_pc = -1;
24 void jtagarm7tdmi_start(void);
26 //! Set a 32-bit ARM register
27 void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
28 //! Get a 32-bit ARM register
29 unsigned long jtagarm7tdmi_get_register(unsigned long reg);
31 // ARM7TDMI-specific pins
32 // DBGRQ - GoodFET Pin 8
36 The instruction register is 4 bits in length.
37 There is no parity bit.
38 The fixed value 0001 is loaded into the instruction register during the CAPTURE-IR
40 The least significant bit of the instruction register is scanned in and scanned out first.
43 //4-bit ARM7TDMI JTAG commands, bit-swapped
44 #define ARM7TDMI_IR_EXTEST 0x0
45 #define ARM7TDMI_IR_SCAN_N 0x2
46 #define ARM7TDMI_IR_SAMPLE 0x3
47 #define ARM7TDMI_IR_RESTART 0x4
48 #define ARM7TDMI_IR_CLAMP 0x5
49 #define ARM7TDMI_IR_HIGHZ 0x7
50 #define ARM7TDMI_IR_CLAMPZ 0x9
51 #define ARM7TDMI_IR_INTEST 0xC
52 #define ARM7TDMI_IR_IDCODE 0xE
53 #define ARM7TDMI_IR_BYPASS 0xF
55 // read 3 bit - Debug Control
56 #define EICE_DBGCTRL 0
57 #define EICE_DBGCTRL_BITLEN 3
58 // read 5 bit - Debug Status
59 #define EICE_DBGSTATUS 1
60 #define EICE_DBGSTATUS_BITLEN 5
61 // read 6 bit - Debug Comms Control Register
63 #define EICE_DBGCCR_BITLEN 6
64 // r/w 32 bit - Debug Comms Data Register
66 // r/w 32 bit - Watchpoint 0 Address
67 #define EICE_WP0ADDR 8
68 // r/w 32 bit - Watchpoint 0 Addres Mask
69 #define EICE_WP0ADDRMASK 9
70 // r/w 32 bit - Watchpoint 0 Data
71 #define EICE_WP0DATA 10
72 // r/w 32 bit - Watchpoint 0 Data Masl
73 #define EICE_WP0DATAMASK 11
74 // r/w 9 bit - Watchpoint 0 Control Value
75 #define EICE_WP0CTRL 12
76 // r/w 8 bit - Watchpoint 0 Control Mask
77 #define EICE_WP0CTRLMASK 13
78 // r/w 32 bit - Watchpoint 0 Address
79 #define EICE_WP1ADDR 16
80 // r/w 32 bit - Watchpoint 0 Addres Mask
81 #define EICE_WP1ADDRMASK 17
82 // r/w 32 bit - Watchpoint 0 Data
83 #define EICE_WP1DATA 18
84 // r/w 32 bit - Watchpoint 0 Data Masl
85 #define EICE_WP1DATAMASK 19
86 // r/w 9 bit - Watchpoint 0 Control Value
87 #define EICE_WP1CTRL 20
88 // r/w 8 bit - Watchpoint 0 Control Mask
89 #define EICE_WP1CTRLMASK 21
92 //JTAGARM7TDMI commands
93 #define JTAGARM7_GET_REGISTER 0x87
94 #define JTAGARM7_SET_REGISTER 0x88
95 #define JTAGARM7_DEBUG_INSTR 0x89
96 // Really ARM specific stuff
97 #define JTAGARM7_SET_IR 0x90
98 #define JTAGARM7_WAIT_DBG 0x91
99 #define JTAGARM7_SHIFT_DR 0x92
100 #define JTAGARM7_CHAIN0 0x93
101 #define JTAGARM7_SCANCHAIN1 0x94
102 #define JTAGARM7_EICE_READ 0x95
103 #define JTAGARM7_EICE_WRITE 0x96
106 // for deeper understanding, read the instruction cycle timing section of:
107 // http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
108 #define EXECNOPARM 0xe1a00000L
109 #define ARM_INSTR_NOP 0xe1a00000L
110 #define ARM_INSTR_BX_R0 0xe12fff10L
111 #define ARM_INSTR_STR_Rx_r14 0xe58f0000L // from atmel docs
112 #define ARM_READ_REG ARM_INSTR_STR_Rx_r14
113 #define ARM_INSTR_LDR_Rx_r14 0xe5900000L // NOT from atmel docs (e59e0000L is from atmel docs)
114 #define ARM_WRITE_REG ARM_INSTR_LDR_Rx_r14
115 #define ARM_INSTR_LDR_R1_r0_4 0xe4901004L
116 #define ARM_READ_MEM ARM_INSTR_LDR_R1_r0_4
117 #define ARM_INSTR_STR_R1_r0_4 0xe4801004L
118 #define ARM_WRITE_MEM ARM_INSTR_STR_R1_r0_4
119 #define ARM_INSTR_MRS_R0_CPSR 0xe10f0000L
120 #define ARM_INSTR_MSR_cpsr_cxsf_R0 0xe12ff000L
121 #define ARM_INSTR_STMIA_R14_r0_rx 0xE88E0000L // add up to 65k to indicate which registers...
122 #define ARM_STORE_MULTIPLE ARM_INSTR_STMIA_R14_r0_rx
123 #define ARM_INSTR_SKANKREGS 0xE88F7fffL
124 #define ARM_INSTR_CLOBBEREGS 0xE89F7fffL
126 #define ARM_INSTR_B_IMM 0xea000000L
127 #define ARM_INSTR_BX_PC 0xe12fff10L // need to set r0 to the desired address
128 #define THUMB_INSTR_LDR_R0_r0 0x68006800L
129 #define THUMB_WRITE_REG THUMB_INSTR_LDR_R0_r0
130 #define THUMB_INSTR_STR_R0_r0 0x60006000L
131 #define THUMB_READ_REG THUMB_INSTR_STR_R0_r0
132 #define THUMB_INSTR_MOV_R0_PC 0x46b846b8L
133 #define THUMB_INSTR_MOV_PC_R0 0x46474647L
134 #define THUMB_INSTR_MOV_HiLo 0x46404640L
135 #define THUMB_INSTR_MOV_LoHi 0x46804680L
136 #define THUMB_INSTR_BX_PC 0x47784778L
137 #define THUMB_INSTR_NOP 0x1c001c00L
138 #define THUMB_SWAP_HiLo 0
139 #define THUMB_SWAP_LoHi 1
140 #define ARM_REG_PC 15
142 #define JTAG_ARM7TDMI_DBG_DBGACK 1
143 #define JTAG_ARM7TDMI_DBG_DBGRQ 2
144 #define JTAG_ARM7TDMI_DBG_IFEN 4
145 #define JTAG_ARM7TDMI_DBG_cgenL 8
146 #define JTAG_ARM7TDMI_DBG_TBIT 16