2 \author Travis Goodspeed
3 \brief MSP430-generic functions.
7 //Silently be empty if not an MSP430.
27 //TODO define differently if needed for telos/apimote
41 //LED2 and LED3 are only used by the telosb and apimote for now
44 PLED2OUT &= ~PLED2PIN;
52 PLED3OUT &= ~PLED3PIN;
59 //! Initialize MSP430 registers and all that jazz.
61 WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
67 /* P5.0 out and low; this is chosen for the PIC app (in which P5.0
68 is !MCLR) to ensure that an attached PIC chip, if present, is
69 immediately driven to reset state. A brief explanation of why this
72 At least dsPIC33F and PIC24H --and very likely other 16-bit PIC
73 families-- draw a large amount of current when running, especially
74 when using a fast clock: from 60 mA up to approx. 90 mA. If the
75 PIC target begins to run before the client can request a new ICSP
76 session, which requires much less current (e.g., less than 2 mA),
77 then the MSP430 chip on the GoodFET will fail to start and the FTDI
78 may have trouble communicating with the client. The latter likely
79 relates to the FTDI on-chip 3V3 regulator being specified up to
83 //P5REN &= ~BIT0; //DO NOT UNCOMMENT. Breaks GF1x support.
85 //This will have to be cut soon. Use pulling resistors instead.
91 //Setup clocks, unique to each '430.
95 //DAC should be at full voltage if it exists.
97 //glitchvoltages(0xfff,0xfff);
98 ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref on
99 //for(i=0;i!=0xFFFF;i++) asm("nop"); //DO NOT UNCOMMENT, breaks GCC4
100 DAC12_0CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; // Int ref gain 1
101 DAC12_0DAT = 0xFFF; //Max voltage 0xfff
102 DAC12_1CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; // Int ref gain 1
103 DAC12_1DAT = 0x000; //Min voltage 0x000
108 This part is really ugly. GSEL (P5.7) must be high to select
109 normal voltage, but a lot of applications light to swing it low
110 to be a nuissance. To get around this, we assume that anyone
111 with a glitching FET will also have a DAC, then we set that DAC
114 At some point, each target must be sanitized to show that it
115 doesn't clear P5OUT or P5DIR.
117 P5DIR|=BIT7; P5OUT=BIT7; //Normal Supply
118 //P5DIR&=~BIT7; //Glitch Supply