1 //! MSP430F1612/1611 clock and I/O definitions
11 unsigned char serial_rx(){
14 while(!(IFG1&URXIFG0));//wait for a byte
22 void serial_tx(unsigned char x){
23 while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
28 void msp430_init_uart(){
32 P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD
36 UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */
39 UTCTL0 = SSEL1; /* UCLK = MCLK */
41 //http://mspgcc.sourceforge.net/baudrate.html
43 UBR00=0x00; UBR10=0x01; UMCTL0=0x00;
45 ME1 &= ~USPIE0; /* USART1 SPI module disable */
46 ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */
50 /* XXX Clear pending interrupts before enable!!! */
53 //IE1 |= URXIE1; /* Enable USART1 RX interrupt */
57 void msp430_init_dco() {
58 /* This code taken from the FU Berlin sources and reformatted. */
59 #define MSP430_CPU_SPEED 2457600UL
60 #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
61 unsigned int compare, oldcapture = 0;
64 WDTCTL = WDTPW + WDTHOLD; //stop WDT
66 BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
67 and SSMCLK. XT2 is off. */
69 BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
70 crystal DCO frquenzy = 2,4576 MHz */
72 BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
73 for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
77 CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
78 TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
83 while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
84 CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
85 compare = CCR2; /* Get current captured SMCLK */
86 compare = compare - oldcapture; /* SMCLK difference */
87 oldcapture = CCR2; /* Save current captured SMCLK */
89 if(DELTA == compare) {
90 break; /* if equal, leave "while(1)" */
91 } else if(DELTA < compare) { /* DCO is too fast, slow it down */
93 if(DCOCTL == 0xFF) { /* Did DCO role under? */
96 } else { /* -> Select next lower RSEL */
98 if(DCOCTL == 0x00) { /* Did DCO role over? */
101 /* -> Select next higher RSEL */
105 CCTL2 = 0; /* Stop CCR2 function */
106 TACTL = 0; /* Stop Timer_A */
108 BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */