1 //! MSP430F1612/1611 clock and I/O definitions
11 unsigned char serial_rx(){
14 while(!(IFG1&URXIFG0));//wait for a byte
22 void serial_tx(unsigned char x){
23 while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
27 //! Set the baud rate.
28 void setbaud(unsigned char rate){
30 //http://mspgcc.sourceforge.net/baudrate.html
33 UBR00=0x7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
36 UBR00=0xBF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
39 UBR00=0x5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
42 UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
46 UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
51 void msp430_init_uart(){
55 P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD
58 UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */
59 UTCTL0 = SSEL1; /* UCLK = MCLK */
63 ME1 &= ~USPIE0; /* USART1 SPI module disable */
64 ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */
68 /* XXX Clear pending interrupts before enable!!! */
72 //IE1 |= URXIE1; /* Enable USART1 RX interrupt */
76 void msp430_init_dco() {
77 /* This code taken from the FU Berlin sources and reformatted. */
81 //#define MSP430_CPU_SPEED 2457600UL
83 //Too fast for internal resistor.
84 //#define MSP430_CPU_SPEED 4915200UL
87 //#deefine MSP430_CPU_SPEED 4500000UL
90 #define MSP430_CPU_SPEED 3683400UL
91 #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
92 unsigned int compare, oldcapture = 0;
95 WDTCTL = WDTPW + WDTHOLD; //stop WDT
101 BCSCTL1 = 0xa8; /* ACLK is devided by 4. RSEL=6 no division for MCLK
102 and SSMCLK. XT2 is off. */
104 BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
105 crystal DCO frquenzy = 2,4576 MHz */
109 BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
110 for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
114 CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
115 TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
120 while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
121 CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
122 compare = CCR2; /* Get current captured SMCLK */
123 compare = compare - oldcapture; /* SMCLK difference */
124 oldcapture = CCR2; /* Save current captured SMCLK */
126 if(DELTA == compare) {
127 break; /* if equal, leave "while(1)" */
128 } else if(DELTA < compare) { /* DCO is too fast, slow it down */
130 if(DCOCTL == 0xFF) { /* Did DCO role under? */
133 } else { /* -> Select next lower RSEL */
135 if(DCOCTL == 0x00) { /* Did DCO role over? */
138 /* -> Select next higher RSEL */
142 CCTL2 = 0; /* Stop CCR2 function */
143 TACTL = 0; /* Stop Timer_A */
145 BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */