1 //! MSP430F1612/1611 clock and I/O definitions
11 unsigned char serial_rx(){
14 while(!(IFG1&URXIFG0));//wait for a byte
22 void serial_tx(unsigned char x){
23 while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
27 //! Set the baud rate.
28 void setbaud(unsigned char rate){
30 //http://mspgcc.sourceforge.net/baudrate.html
35 UBR00=0x00; UBR10=0x01; UMCTL0=0x00;
38 UBR00=0x00; UBR10=0x02; UMCTL0=0x00;
41 UBR00=0x40; UBR10=0x00; UMCTL0=0x00;
50 void msp430_init_uart(){
54 P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD
57 UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */
58 UTCTL0 = SSEL1; /* UCLK = MCLK */
62 ME1 &= ~USPIE0; /* USART1 SPI module disable */
63 ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */
67 /* XXX Clear pending interrupts before enable!!! */
71 //IE1 |= URXIE1; /* Enable USART1 RX interrupt */
75 void msp430_init_dco() {
76 /* This code taken from the FU Berlin sources and reformatted. */
77 #define MSP430_CPU_SPEED 2457600UL
78 #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
79 unsigned int compare, oldcapture = 0;
82 WDTCTL = WDTPW + WDTHOLD; //stop WDT
84 BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
85 and SSMCLK. XT2 is off. */
87 BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
88 crystal DCO frquenzy = 2,4576 MHz */
90 BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
91 for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
95 CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
96 TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
101 while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
102 CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
103 compare = CCR2; /* Get current captured SMCLK */
104 compare = compare - oldcapture; /* SMCLK difference */
105 oldcapture = CCR2; /* Save current captured SMCLK */
107 if(DELTA == compare) {
108 break; /* if equal, leave "while(1)" */
109 } else if(DELTA < compare) { /* DCO is too fast, slow it down */
111 if(DCOCTL == 0xFF) { /* Did DCO role under? */
114 } else { /* -> Select next lower RSEL */
116 if(DCOCTL == 0x00) { /* Did DCO role over? */
119 /* -> Select next higher RSEL */
123 CCTL2 = 0; /* Stop CCR2 function */
124 TACTL = 0; /* Stop Timer_A */
126 BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */