DP_SELECT_OFF = 0x8
DP_RDBUFF_OFF = 0xC
+MAX_AP_COUNT = 16
+
PM_usr = 0b10000
PM_fiq = 0b10001
PM_irq = 0b10010
ORUNDETECT = 1<<0
-
def debugstr(strng):
print >>sys.stderr,(strng)
def PSRdecode(psrval):
self.ir_status = None
self.ap_selected = None
self.ap_bank = 0
- self.aps = []
+ self.aps = None
def __del__(self):
pass
apsel = raw>>24
return "SWDP_CTRLSEL = %d\nAPBANKSEL = %d\nAPSEL = %d\n"
+ def ADIgetAccessPorts(self):
+ if self.aps == None:
+ self.aps = [createAP(self, x) for x in xrange(MAX_AP_COUNT)]
+ return self.aps
+
def ADIgetWCR(self): # SWDP only
raise Exception("IMPLEMENT ME: ADIgetWCR")
return self.ADIgetDPACC(0x8)
return self.ap_selected
-
+def createAP(dp, apnum):
+ idr = 0xfc
+ bank = idr/16
+ self.dp.ADIsetSELECT(self.apnum, bank)
+ ident = self.dp.ADIgetAPACC(idr&0xf)
+ if ((ident>>16)&1):
+ return ADI_MEM_AP(dp, apnum)
+ return ADI_JTAG_AP(dp, apnum)
class ADI_AccessPort: # define common AP calls
def __init__(self, DP, apnum):
#def
class ADI_MEM_AP(ADI_AccessPort):
+ MEMAP_CSW_REG = 0x0
+ MEMAP_TAR_REG = 0x4
+ MEMAP_DRW_REG = 0xC
+ MEMAP_BD0 = 0x10
+ MEMAP_BD1 = 0x14
+ MEMAP_BD2 = 0x18
+ MEMAP_BD3 = 0x1C
+ MEMAP_CFG_REG = 0xF4
+ MEMAP_BASE_REG = 0xF8
+ MEMAP_IDR_REG = 0xFC
+
def __init__(self, DP, apnum):
ADI_AccessPort.__init__(self, DP, apnum)
self.cfg = self.getCFG() # necessary to cache endianness information
# FIXME: how do i determine if this adi supports multibyte access or just word? or packed transfers?
self.setMemAccessSize(4)
- def setMemAccessSize(self, bytecount):
- csw = self.getCSW()
- csw &= 0xfffffff8
- csw |= (bytecount>>1)
- self.setCSW(csw)
-
def getCSW(self):
- pass
+ """ Control/Status Word reg """
+ return self.getRegister(self.MEMAP_CSW_REG)
def setCSW(self, csw):
- pass
+ """ Control/Status Word reg. Some bits are RO """
+ return self.setRegister(self.MEMAP_CSW_REG, csw)
+ def reprCSW(self):
+ csw = self.getCSW()
+
def getTAR(self):
- pass
- def setTAR(self, csw):
- pass
+ """ Transfer Address Register. Used for both DRW and BDx accesses. Autoinc (see CSW) only works for DRW accesses, not Banked Regs"""
+ return self.getRegister(self.MEMAP_TAR_REG)
+ def setTAR(self, tar):
+ """ Transfer Address Register. Used for both DRW and BDx accesses. Autoinc (see CSW) only works for DRW accesses, not Banked Regs"""
+ return self.setRegister(self.MEMAP_TAR_REG, tar)
def getDRW(self):
- pass
- def setDRW(self, csw):
- pass
+ """ Data Read/Write reg. """
+ return self.getRegister(self.MEMAP_DRW_REG)
+ def setDRW(self, drw):
+ """ Data Read/Write reg. """
+ return self.setRegister(self.MEMAP_DRW_REG, drw)
+
+ #FIXME: use one set of accessors... either keep the indexed version or the individuals.
+ def getBDReg(self, index):
+ return self.getRegister(self.MEMAP_BD0_REG + (index*4))
+ def setBDReg(self, index, bd):
+ return self.setRegister(self.MEMAP_BD0_REG + (index*4), bd0)
def getBD0(self):
- pass
- def setBD0(self, csw):
- pass
+ return self.getRegister(self.MEMAP_BD0_REG)
+ def setBD0(self, bd0):
+ return self.setRegister(self.MEMAP_BD0_REG, bd0)
+
+ def getBD1(self):
+ return self.getRegister(self.MEMAP_BD1_REG)
+ def setBD1(self, bd1):
+ return self.setRegister(self.MEMAP_BD1_REG, bd1)
+
+ def getBD2(self):
+ return self.getRegister(self.MEMAP_BD2_REG)
+ def setBD2(self, bd2):
+ return self.setRegister(self.MEMAP_BD2_REG, bd2)
+
+ def getBD3(self):
+ return self.getRegister(self.MEMAP_BD3_REG)
+ def setBD3(self, bd3):
+ return self.setRegister(self.MEMAP_BD3_REG, bd3)
def getCFG(self):
- pass
- def setCFG(self, csw):
- pass
+ return self.getRegister(self.MEMAP_CFG_REG)
+ def setCFG(self, cfg):
+ return self.setRegister(self.MEMAP_CFG_REG, cfg)
def getBASE(self):
- pass
- def setBASE(self, csw):
- pass
+ """ BASE debug address. RO """
+ return self.getRegister(self.MEMAP_BASE_REG)
+ def setBASE(self, base):
+ """ BASE debug address. RO """
+ return self.setRegister(self.MEMAP_BASE_REG, base)
def getIDR(self):
- pass
- def setIDR(self, csw):
- pass
+ return self.getRegister(self.MEMAP_IDR_REG)
+
+ # CFG accessors
+ CFG_DBGSWENABLE_BITS = 31
+ CFG_DBGSWENABLE = 1<<31
+ CFG_PROT_BITS = 24
+ CFG_PROT = 0x3f<<24
+ CFG_SPIDEN_BITS = 23
+ CFG_SPIDEN = 1<<23
+ CFG_MODE_BITS = 8
+ CFG_MODE = 0xf<<8
+ CFG_TRINPROG_BITS = 7
+ CFG_TRINPROG = 1<<7
+ CFG_DEVICEEN_BITS = 6
+ CFG_DEVICEEN = 1<<6
+ CFG_ADDRINC_BITS = 4
+ CFG_ADDRINC = 3<<4
+ CFG_SIZE_BITS = 0
+ CFG_SIZE = 7
+ CFG_ADDRINC_off = 0b00
+ CFG_ADDRINC_single = 0b01
+ CFG_ADDRINC_packed = 0b10
+ CFG_MEM_8bits = 0b000
+ CFG_MEM_16bits = 0b001
+ CFG_MEM_32bits = 0b010
+ def CSWsetDbgSwEnable(self, bit):
+ cfg = self.getCFG() & self.CFG_DBGSWENABLE
+ cfg |= (bit<<self.CFG_DBGSWENABLE_BITS)
+ def CSWgetDbgSwEnable(self):
+ cfg = (self.getCFG() & self.CFG_DBGSWENABLE) >> self.CFG_DBGSWENABLE_BITS
+ return cfg
+
+ def CSWsetAddrInc(self, bits=CFG_ADDRINC_single):
+ cfg = (self.getCFG() & self.CFG_ADDRINC) >> self.CFG_ADDRINC_BITS
+ cfg |= (bit<<self.CFG_DBGSWENABLE_BITS)
+ def CSWsetMemAccessSize(self, bytecount=self.CSW_MEM_32bits): # 0b010 == 32bit words, necessary if the implementation allows for variable sizes
+ csw = self.getCSW()
+ csw &= 0xfffffff8
+ csw |= (bytecount>>1)
+ self.setCSW(csw)
+
+
+
projects / goodfet / blobdiff