+ return self.getRegister(self.MEMAP_IDR_REG)
+
+ # CFG accessors
+ CFG_DBGSWENABLE_BITS = 31
+ CFG_DBGSWENABLE = 1<<31
+ CFG_PROT_BITS = 24
+ CFG_PROT = 0x3f<<24
+ CFG_SPIDEN_BITS = 23
+ CFG_SPIDEN = 1<<23
+ CFG_MODE_BITS = 8
+ CFG_MODE = 0xf<<8
+ CFG_TRINPROG_BITS = 7
+ CFG_TRINPROG = 1<<7
+ CFG_DEVICEEN_BITS = 6
+ CFG_DEVICEEN = 1<<6
+ CFG_ADDRINC_BITS = 4
+ CFG_ADDRINC = 3<<4
+ CFG_SIZE_BITS = 0
+ CFG_SIZE = 7
+ CFG_ADDRINC_off = 0b00
+ CFG_ADDRINC_single = 0b01
+ CFG_ADDRINC_packed = 0b10
+ CFG_MEM_8bits = 0b000
+ CFG_MEM_16bits = 0b001
+ CFG_MEM_32bits = 0b010
+ def CSWsetDbgSwEnable(self, bit):
+ cfg = self.getCFG() & self.CFG_DBGSWENABLE
+ cfg |= (bit<<self.CFG_DBGSWENABLE_BITS)
+ def CSWgetDbgSwEnable(self):
+ cfg = (self.getCFG() & self.CFG_DBGSWENABLE) >> self.CFG_DBGSWENABLE_BITS
+ return cfg
+
+ def CSWsetAddrInc(self, bits=CFG_ADDRINC_single):
+ cfg = (self.getCFG() & self.CFG_ADDRINC) >> self.CFG_ADDRINC_BITS
+ cfg |= (bit<<self.CFG_DBGSWENABLE_BITS)
+ def CSWsetMemAccessSize(self, bytecount=self.CSW_MEM_32bits): # 0b010 == 32bit words, necessary if the implementation allows for variable sizes
+ csw = self.getCSW()
+ csw &= 0xfffffff8
+ csw |= (bytecount>>1)
+ self.setCSW(csw)
+
+
+