#!/usr/bin/env python
# GoodFET ARM Client Library
#
-#
-# Good luck with alpha / beta code.
# Contributions and bug reports welcome.
#
# todo:
# * ensure correct PC handling
# * flash manipulation (probably need to get the specific chip for this one)
# * set security (chip-specific)
-# * -ancilary/faster- ldm/stm versions of memory access (had trouble in past, possibly also due to haphazard abuse of DCLK)
-#
-# fixme now stuff:
-# * thumb mode get/set_register - DONE!
-# * thumb to arm mode - DONE!
-# * rethink the whole python/c trade-off for cross-python session debugging
import sys, binascii, struct, time
-import atlasutils.smartprint as asp
from GoodFET import GoodFET
from intelhex import IntelHex
DR_SHIFT = 0x81
RESETTAP = 0x82
RESETTARGET = 0x83
-GET_REGISTER = 0x87
-SET_REGISTER = 0x88
-DEBUG_INSTR = 0x89
+DR_SHIFT_MORE = 0x87
+GET_REGISTER = 0x8d
+SET_REGISTER = 0x8e
+DEBUG_INSTR = 0x8f
# Really ARM specific stuff
WAIT_DBG = 0x91
CHAIN0 = 0x93
ARM_READ_MEM = ARM_INSTR_LDR_R1_r0_4
ARM_INSTR_STR_R1_r0_4 = 0xe4801004L
ARM_WRITE_MEM = ARM_INSTR_STR_R1_r0_4
+ARM_INSTR_STRB_R1_r0_1 = 0xe4c01001L
+ARM_WRITE_MEM_BYTE = ARM_INSTR_STRB_R1_r0_1
ARM_INSTR_MRS_R0_CPSR = 0xe10f0000L
ARM_INSTR_MSR_cpsr_cxsf_R0 =0xe12ff000L
ARM_INSTR_STMIA_R14_r0_rx = 0xE88e0000L # add up to 65k to indicate which registers...
"""Move the FET into the JTAG ARM application."""
#print "Initializing ARM."
self.writecmd(0x13,SETUP,0,self.data)
- def getpc(self):
- return self.ARMgetPC()
def flash(self,file):
"""Flash an intel hex file to code memory."""
print "Flash not implemented.";
- def dump(self,file,start=0,stop=0xffff):
+ def dump(self,fn,start=0,stop=0xffffffff):
"""Dump an intel hex file from code memory."""
+
+ print "Dumping from %04x to %04x as %s." % (start,stop,f);
+ # FIXME: get mcu state and return it to that state
+ self.halt()
+
+ h = IntelHex(None);
+ i=start;
+ while i<=stop:
+ data=self.ARMreadChunk(i, 48, verbose=0);
+ print "Dumped %06x."%i;
+ for dword in data:
+ if i<=stop and dword != 0xdeadbeef:
+ h.puts( i, struct.pack("<I", dword) )
+ i+=4;
+ # FIXME: get mcu state and return it to that state
+ self.resume()
+ h.write_hex_file(fn);
+
print "Dump not implemented.";
def ARMshift_IR(self, IR, noretidle=0):
self.writecmd(0x13,IR_SHIFT,2, [IR, LSB|noretidle])
return self.data
def ARMshift_DR(self, data, bits, flags):
- self.writecmd(0x13,DR_SHIFT,8,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff])
+ self.writecmd(0x13,DR_SHIFT,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff])
+ return self.data
+ def ARMshift_DR_more(self, data, bits, flags):
+ self.writecmd(0x13,DR_SHIFT_MORE,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff])
return self.data
def ARMwaitDBG(self, timeout=0xff):
self.current_dbgstate = self.ARMget_dbgstate()
return retval
def ARMidentstr(self):
ident=self.ARMident()
- ver = ident >> 28
- partno = (ident >> 12) & 0x10
- mfgid = ident & 0xfff
- return "mfg: %x\npartno: %x\nver: %x\n(%x)" % (ver, partno, mfgid, ident);
+ ver = (ident >> 28)
+ partno = (ident >> 12) & 0xffff
+ mfgid = (ident >> 1) & 0x7ff
+ return "Chip IDCODE: 0x%x\n\tver: %x\n\tpartno: %x\n\tmfgid: %x\n" % (ident, ver, partno, mfgid);
def ARMeice_write(self, reg, val):
data = chop(val,4)
data.extend([reg])
def ARMgetPC(self):
"""Get an ARM's PC. Note: real PC gets all wonky in debug mode, this is the "saved" PC"""
return self.storedPC
+ getpc = ARMgetPC
def ARMsetPC(self, val):
"""Set an ARM's PC. Note: real PC gets all wonky in debug mode, this changes the "saved" PC which is used when exiting debug mode"""
self.storedPC = val
instr.extend([bkpt])
self.writecmd(0x13,DEBUG_INSTR,len(instr),instr)
return (self.data)
- def ARM_nop(self, bkpt):
+ def ARM_nop(self, bkpt=0):
if self.status() & DBG_TBIT:
return self.ARMdebuginstr(THUMB_INSTR_NOP, bkpt)
return self.ARMdebuginstr(ARM_INSTR_NOP, bkpt)
self.ARMsetModeARM()
# branch to the right address
self.ARMset_register(15, self.storedPC)
- print hex(self.storedPC)
- print hex(self.ARMget_register(15))
- print hex(self.ARMchain0(self.storedPC,self.flags)[0])
+ #print hex(self.storedPC)
+ #print hex(self.ARMget_register(15))
+ #print hex(self.ARMchain0(self.storedPC,self.flags)[0])
+ self.ARMchain0(self.storedPC,self.flags)
self.ARM_nop(0)
self.ARM_nop(1)
self.ARMdebuginstr(ARM_INSTR_B_IMM | 0xfffff0,0)
self.ARMdebuginstr(THUMB_INSTR_MOV_PC_R0,0)
self.ARM_nop(0)
self.ARM_nop(1)
- print hex(self.storedPC)
- print hex(self.ARMget_register(15))
+ #print hex(self.storedPC)
+ #print hex(self.ARMget_register(15))
print hex(self.ARMchain0(self.storedPC,self.flags)[0])
self.ARMdebuginstr(THUMB_INSTR_B_IMM | (0x7fc07fc),0)
- self.ARM_nop()
+ self.ARM_nop(0)
self.ARMrestart()
self.ARM_nop(0)
self.ARMrestart()
self.ARMwaitDBG()
- print hex(self.ARMget_register(1))
+ #print hex(self.ARMget_register(1))
# FIXME: this may end up changing te current debug-state. should we compare to current_dbgstate?
#print repr(self.data[4])
self.ARMset_register(1, r1); # restore R0 and R1
self.ARMset_register(0, r0);
return retval
- def ARMreadChunk(self, adr, wordcount):
+ def ARMreadChunk(self, adr, wordcount, verbose=1):
""" Only works in ARM mode currently
WARNING: Addresses must be word-aligned!
"""
output = []
count = wordcount
while (wordcount > 0):
+ if (verbose and wordcount%64 == 0): sys.stderr.write(".")
count = (wordcount, 0xe)[wordcount>0xd]
bitmask = LDM_BITMASKS[count]
self.ARMset_register(14,adr)
regs = self.ARMget_registers()
wordcount = len(wordarray)
while (wordcount > 0):
+ if (wordcount%64 == 0): sys.stderr.write(".")
count = (wordcount, 0xe)[wordcount>0xd]
bitmask = LDM_BITMASKS[count]
self.ARMset_register(14,adr)
- print len(wordarray),bin(bitmask)
+ #print len(wordarray),bin(bitmask)
self.ARMset_registers(wordarray[:count],bitmask)
self.ARM_nop(1)
self.ARMdebuginstr(ARM_INSTR_STMIA_R14_r0_rx | bitmask ,0)
wordarray = wordarray[count:]
wordcount -= count
adr += count*4
- print hex(adr)
+ #print hex(adr)
# FIXME: handle the rest of the wordcount here.
- def ARMwriteMem(self, adr, wordarray):
+ def ARMwriteMem(self, adr, wordarray, instr=ARM_WRITE_MEM):
r0 = self.ARMget_register(0); # store R0 and R1
r1 = self.ARMget_register(1);
#print >>sys.stderr,("CPSR:\t%x"%self.ARMget_regCPSR())
self.ARMset_register(1, word); # write address into R0
self.ARM_nop(0)
self.ARM_nop(1)
- self.ARMdebuginstr(ARM_WRITE_MEM, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes)
+ self.ARMdebuginstr(instr, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes)
self.ARM_nop(0)
self.ARMrestart()
self.ARMwaitDBG()
- print hex(self.ARMget_register(1))
+ #print >>sys.stderr,hex(self.ARMget_register(1))
self.ARMset_register(1, r1); # restore R0 and R1
self.ARMset_register(0, r0);
+ def writeMemByte(self, adr, byte):
+ self.ARMwriteMem(adr, byte, ARM_WRITE_MEM_BYTE)
+
ARMstatusbits={
0x10 : "TBIT",
bulk = chop(address,4)
bulk.extend(chop(bits,8))
bulk.extend(chop(data,4))
- print (repr(bulk))
+ #print >>sys.stderr,(repr(bulk))
self.writecmd(0x13,CHAIN0,16,bulk)
d1,b1,a1 = struct.unpack("<LQL",self.data)
return (a1,b1,d1)
+
def start(self):
"""Start debugging."""
self.writecmd(0x13,START,0,self.data)
+ print >>sys.stderr,"Identifying Target:"
ident=self.ARMidentstr()
- print "Target identifies as %s." % ident
- print "Debug Status: %s." % self.statusstr()
- #print "System State: %x." % self.ARMget_regCPSRstr()
+ print >>sys.stderr,ident
+ print >>sys.stderr,"Debug Status:\t%s\n" % self.statusstr()
+
def stop(self):
"""Stop debugging."""
self.writecmd(0x13,STOP,0,self.data)
projects / goodfet / blobdiff