Dropped ugly 'blocks' kludge for a 16-bit length field.

[goodfet] / firmware / apps / chipcon / chipcon.c

diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c
index 3aebe1e..05349ea 100644 (file)
--- a/firmware/apps/chipcon/chipcon.c
+++ b/firmware/apps/chipcon/chipcon.c
@@ -1,11 +1,12 @@
-//GoodFET ChipCon Debugging Application
-//by Travis Goodspeed
-//<travis at radiantmachines.com>
+/*! \file chipcon.c
+  \author Travis Goodspeed
+  \brief Chipcon 8051 debugging.
+*/
 
 
 //This is like SPI, except that you read or write, not both.
 
-/** N.B. The READ verb performs a write of all (any) supplied data,
+/* N.B. The READ verb performs a write of all (any) supplied data,
     then reads a single byte reply from the target.  The WRITE verb
     only writes.
 */
@@ -19,7 +20,7 @@
 #include <iomacros.h>
 
 
-/** Concerning clock rates,
+/* Concerning clock rates,
     the maximimum clock rates are defined on page 4 of the spec.
     They vary, but are roughly 30MHz.  Raising this clock rate might
     allow for clock glitching, but the GoodFET isn't sufficient fast for that.
@@ -123,7 +124,7 @@ void ccread(unsigned char len){
 //! Handles a monitor command.
 void cchandle(unsigned char app,
               unsigned char verb,
-              unsigned char len){
+              unsigned long len){
   switch(verb){
     //CC_PEEK and CC_POKE will come later.
   case READ:  //Write a command and return 1-byte reply.
@@ -215,7 +216,6 @@ void cchandle(unsigned char app,
     txdata(app,verb,1);
     break;
   case CC_SET_PC:
-    
   case CC_CLOCK_INIT:
   case CC_WRITE_FLASH_PAGE:
   case CC_MASS_ERASE_FLASH:
@@ -360,7 +360,7 @@ unsigned char cc_peekcodebyte(unsigned long adr){
   //CLR A
   cc_debug(2, 0xE4, 0, 0);
   //MOVC A, @A+DPTR;
-  toret=cc_debug(1, 0x93, 0, 0);
+  toret=cc_debug(3, 0x93, 0, 0);
   //INC DPTR
   //cc_debug(1, 0xA3, 0, 0);