+
+#if (platform == tilaunchpad)
+/*
+ * The Launchpad has only pins easily available
+ * P5.3 TCK SCK (labeled TEST J3-10 J2-17) DC closest to antenna (blue)
+ * P5.2 IO MISO MOSI (labeled RST J3-8 J2-16) DD next to closer to USB (yellow)
+ * P3.6 txd1 RST (labeled RXD J3-6 J1-4) next to GND, which is closest to USB (orange)
+ * P3.7 rxd1 RST (labeled TXD J3-4 J1-3) connect to led1 J1-2
+ *
+ * for a permanent marriage between a TI-Launchpad, move RST to pin48 P5.4
+ * (requeries soldering) and use rxd/txd for direct communication with IM-ME dongle.
+ */
+
+#define RST BIT6 // P3.7
+#include <msp430_serial.h>
+#else // tilaunchpad
+#if (platform == tilaunchpad)
+# if (SPIDIR != P5DIR)
+# error "SPIDIR != P5DIR"
+# endif
+# if (SPIOUT != P5OUT)
+# error "SPIOUT != P5OUT"
+# endif
+# define SETRST P3OUT|=RST
+# define CLRRST P3OUT&=~RST
+#else
+# define SETRST P3OUT|=RST
+# define CLRRST P3OUT&=~RST
+#endif
+
#define CCWRITE SPIDIR|=MOSI
#define CCREAD SPIDIR&=~MISO
//! Set up the pins for CC mode. Does not init debugger.
void ccsetup(){
#define CCWRITE SPIDIR|=MOSI
#define CCREAD SPIDIR&=~MISO
//! Set up the pins for CC mode. Does not init debugger.
void ccsetup(){
14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
18: d2 c3 31 00 bic.b #1, &0x0031 ;4
1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
18: d2 c3 31 00 bic.b #1, &0x0031 ;4
1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
24: f2 e2 31 00 xor.b #8, &0x0031 ;4
28: f2 e2 31 00 xor.b #8, &0x0031 ;4
2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
24: f2 e2 31 00 xor.b #8, &0x0031 ;4
28: f2 e2 31 00 xor.b #8, &0x0031 ;4
2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
//Two positive debug clock pulses while !RST is low.
//Take RST low, pulse twice, then high.
SPIOUT&=~SCK;
delay(10);
//Two positive debug clock pulses while !RST is low.
//Take RST low, pulse twice, then high.
SPIOUT&=~SCK;
delay(10);
//Return that many bytes.
for(i=0;i<blocklen;i++)
cmddata[i]=cc_peekdatabyte(blockadr+i);
txdata(app,verb,blocklen);
break;
//Return that many bytes.
for(i=0;i<blocklen;i++)
cmddata[i]=cc_peekdatabyte(blockadr+i);
txdata(app,verb,blocklen);
break;
case CC_WRITE_XDATA_MEMORY:
cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
txdata(app,verb,1);
case CC_WRITE_XDATA_MEMORY:
cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
txdata(app,verb,1);
- 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
+ 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
- 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
- // ; Wait for flash erase to complete
- 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
- 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
-
+ 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
+ // ; Wait for flash erase to complete
+ 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
+ 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
+
- // ; Initialize the data pointer
- 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
- // ; Outer loops
- 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
- 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
- 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
- // ; Inner loops
+ // ; Initialize the data pointer
+ 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
+ // ; Outer loops
+ 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
+ 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
+ 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
+ // ; Inner loops
- 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
- 0xE0, // writeWordLoop: MOVX A, @DPTR;
- 0xA3, // INC DPTR;
- 0xF5, 0xAF, // MOV FWDATA, A;
- 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
- // ; Wait for completion
- 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
- 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
- 0xDE, 0xF1, // DJNZ R6, writeLoop;
- 0xDF, 0xEF, // DJNZ R7, writeLoop;
- // ; Done, fake a breakpoint
- 0xA5 // DB 0xA5;
+ 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
+ 0xE0, // writeWordLoop: MOVX A, @DPTR;
+ 0xA3, // INC DPTR;
+ 0xF5, 0xAF, // MOV FWDATA, A;
+ 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
+ // ; Wait for completion
+ 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
+ 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
+ 0xDE, 0xF1, // DJNZ R6, writeLoop;
+ 0xDF, 0xEF, // DJNZ R7, writeLoop;
+ // ; Done, fake a breakpoint
+ 0xA5 // DB 0xA5;
void cc_write_flash_page(u32 adr){
//Assumes that page has already been written to XDATA 0xF000
//debugstr("Flashing 2kb at 0xF000 to given adr.");
void cc_write_flash_page(u32 adr){
//Assumes that page has already been written to XDATA 0xF000
//debugstr("Flashing 2kb at 0xF000 to given adr.");
if(flash_word_size!=2 && flash_word_size!=4){
debugstr("Flash word size is wrong, aborting write to");
debughex(adr);
while(1);
}
if(flash_word_size!=2 && flash_word_size!=4){
debugstr("Flash word size is wrong, aborting write to");
debughex(adr);
while(1);
}
//Routine comes next
//WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
//Routine comes next
//WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
debugstr("Ugly patching code failing in chipcon.c");
cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
flash_word_size);
debugstr("Ugly patching code failing in chipcon.c");
cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
flash_word_size);
//MOV MEMCTR, (bank*16)+1
cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
//MOV DPTR, address
cc_debug(3, 0x90, hb, lb);
//MOV MEMCTR, (bank*16)+1
cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
//MOV DPTR, address
cc_debug(3, 0x90, hb, lb);
toret=cc_debug(3, 0x93, 0, 0);
//INC DPTR
//cc_debug(1, 0xA3, 0, 0);
toret=cc_debug(3, 0x93, 0, 0);
//INC DPTR
//cc_debug(1, 0xA3, 0, 0);
//MOV DPTR, adr
cc_debug(3, 0x90, hb, lb);
//MOV A, val
cc_debug(2, 0x74, val, 0);
//MOVX @DPTR, A
cc_debug(1, 0xF0, 0, 0);
//MOV DPTR, adr
cc_debug(3, 0x90, hb, lb);
//MOV A, val
cc_debug(2, 0x74, val, 0);
//MOVX @DPTR, A
cc_debug(1, 0xF0, 0, 0);