Chipcon entry in ASM.

[goodfet] / firmware / apps / chipcon / chipcon.c

diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c
index 8d4abca..ce0a9ff 100644 (file)
--- a/firmware/apps/chipcon/chipcon.c
+++ b/firmware/apps/chipcon/chipcon.c
@@ -56,12 +56,28 @@ void ccsetup(){
   //P5REN=0xFF;
 }
 
+
+/* 33 cycle critical region
+0000000e <ccdebuginit>:
+   e:  f2 d0 0d 00     bis.b   #13,    &0x0031 ;5 cycles
+  12:  31 00 
+  14:  f2 c2 31 00     bic.b   #8,     &0x0031 ;4 cycles
+  18:  d2 c3 31 00     bic.b   #1,     &0x0031 ;4
+  1c:  f2 e2 31 00     xor.b   #8,     &0x0031 ;4
+  20:  f2 e2 31 00     xor.b   #8,     &0x0031 ;4
+  24:  f2 e2 31 00     xor.b   #8,     &0x0031 ;4
+  28:  f2 e2 31 00     xor.b   #8,     &0x0031 ;4
+  2c:  d2 d3 31 00     bis.b   #1,     &0x0031 ;4
+  30:  30 41           ret                     
+*/
+
+/*
 //! Initialize the debugger
 void ccdebuginit(){
   //Port output BUT NOT DIRECTION is set at start.
   P5OUT|=MOSI+SCK+RST;
   
-  delay(30); //So the beginning is ready for glitching.
+  //delay(30); //So the beginning is ready for glitching.
   
   //Two positive debug clock pulses while !RST is low.
   //Take RST low, pulse twice, then high.
@@ -78,6 +94,10 @@ void ccdebuginit(){
   //Raise !RST.
   P5OUT|=RST;
 }
+*/
+
+//! Initialize the debugger.
+void ccdebuginit(); 
 
 //! Read and write a CC bit.
 unsigned char cctrans8(unsigned char byte){
@@ -154,7 +174,6 @@ void cchandle(unsigned char app,
     txdata(app,verb,0);
     break;
   case START://enter debugger
-    //ccsetup(); //interferes with glitching
     ccdebuginit();
     txdata(app,verb,0);
     break;