WDTCTL = WDTPW + WDTHOLD; // Stop WDT
TACTL = TASSEL1 + TACLR; // SMCLK, clear TAR
CCTL0 = CCIE; // CCR0 interrupt enabled
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
TACTL = TASSEL1 + TACLR; // SMCLK, clear TAR
CCTL0 = CCIE; // CCR0 interrupt enabled
break;
case GLITCHTIME:
_DINT();//disable interrupts
TACTL=0; //clear dividers
TACTL|=TACLR; //clear config
TACTL|=TASSEL_SMCLK| //smclk source
break;
case GLITCHTIME:
_DINT();//disable interrupts
TACTL=0; //clear dividers
TACTL|=TACLR; //clear config
TACTL|=TASSEL_SMCLK| //smclk source
glitchvoltages(0xFFF,0);//Inverted VCC and GND.
P5OUT|=BIT7;//Normal
P5DIR|=BIT7;
while(1){
P5OUT&=~BIT7;//Glitch
//asm("nop");//asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");
glitchvoltages(0xFFF,0);//Inverted VCC and GND.
P5OUT|=BIT7;//Normal
P5DIR|=BIT7;
while(1){
P5OUT&=~BIT7;//Glitch
//asm("nop");//asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");
P5OUT|=BIT7;//Normal
asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");
P5OUT|=BIT7;//Normal
asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");asm("nop");