Bit of rearranging of Chipcon support.

[goodfet] / firmware / apps / glitch / glitch.c

diff --git a/firmware/apps/glitch/glitch.c b/firmware/apps/glitch/glitch.c
index b5cd5bc..f337e42 100644 (file)
--- a/firmware/apps/glitch/glitch.c
+++ b/firmware/apps/glitch/glitch.c
@@ -15,20 +15,11 @@
 //! Call this before the function to be glitched.
 void glitchprime(){
 #ifdef DAC12IR
-  //Don't forget to call glitchvoltages().
-  
-  //Reconfigure TACTL.
-  TACTL=0;           //Clear dividers.
-  TACTL|=TACLR;      //Clear TimerA Config
-  TACTL|=
-    TASSEL_SMCLK |   //SMCLK source,
-    MC_1 |            //Count up to CCR0
-    TAIE;            //Enable Interrupt
-  CCTL0 = CCIE;                         // CCR0 interrupt enabled
-  CCR0 = glitchcount;
+  WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
   
-  //Enable general interrupts, just in case.
+  glitchsetup();
   _EINT();
+  return;
 #endif
 }
 
@@ -36,35 +27,35 @@ void glitchprime(){
 void glitchsetup(){
 #ifdef DAC12IR
   //Set GSEL high to disable glitching.
-
-  P5DIR|=0x80;
-  P6DIR|=BIT6+BIT5;
   
-  P5OUT|=0x80;
+  //Normal voltage, use resistors instead of output.
+  P5DIR=0x80;   //ONLY glitch pin is output.
+  P5OUT|=0x80;  //It MUST begin high.
+  P5REN|=0xFF;  //Resistors pull high and low weakly.
+  
+  P6DIR|=BIT6+BIT5;
   P6OUT|=BIT6+BIT5;
-
+  
   WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
   TACTL = TASSEL1 + TACLR;              // SMCLK, clear TAR
   CCTL0 = CCIE;                         // CCR0 interrupt enabled
-  CCR0 = glitchcount;
-  TACTL |= MC1;                         // Start Timer_A in continuous mode
+  CCR0 = glitchcount+0x15; //clock divider
+  TACTL |= MC_3;
   _EINT();                              // Enable interrupts 
 #endif
 }
 
 // Timer A0 interrupt service routine
-interrupt(TIMERA0_VECTOR) Timer_A (void)
-{
-#ifdef DAC12IR
+interrupt(TIMERA0_VECTOR) Timer_A (void){
   P5OUT&=~BIT7;//Glitch
+  //P5DIR=BIT7; //All else high impedance.
   P5OUT|=BIT7;//Normal
-#endif
-  TACTL |= MC0;                         // Stop Timer_A;
+  TACTL |= MC0;// Stop Timer_A;
+  
+  return;
 }
 
 
-
-
 u16 glitchcount=0;
 
 //! Glitch an application.
@@ -76,7 +67,15 @@ void glitchapp(u8 app){
 //! Set glitching voltages.
 void glitchvoltages(u16 gnd, u16 vcc){
   int i;
-  //debugstr("Set glitching voltages.");
+  //debugstr("Set glitching voltages: GND and VCC");
+  //debughex(gnd);
+  //debughex(vcc);
+  
+  /** N.B., because this is confusing as hell.  As per Page 86 of
+      SLAS541F, P6SEL is not what controls the use of the DAC0/DAC1
+      functions on P6.6 and P6.5.  Instead, CAPD or DAC12AMP>0 sets
+      the state.
+  */
   
   #ifdef DAC12IR
   ADC12CTL0 = REF2_5V + REFON;                  // Internal 2.5V ref on
@@ -98,6 +97,7 @@ void glitchrate(u16 rate){
 void glitchhandle(unsigned char app,
                  unsigned char verb,
                  unsigned long len){
+  P1OUT&=~1;
   switch(verb){
   case GLITCHVOLTAGES:
     glitchvoltages(cmddataword[0],