jtag_ir_shift8(IR_DATA_TO_ADDR);
jtag_dr_shift16(data);
SETTCLK;
+}
+
+//! Defined in jtag430asm.S
+void jtag430_tclk_flashpulses(int);
+/* //! Pulse TCLK at 350kHz +/- 100kHz */
+/* void jtag430_tclk_flashpulses(register i){ */
+/* //TODO check this on a scope. */
+/* register j=0; */
+
+/* //At 2MHz, 350kHz is obtained with 5 clocks of delay */
+
+/* /\** Pondering: */
+/* What happens if the frequency is too low or to high? */
+/* Is there any risk of damaging the chip, or only of a poor write? */
+/* *\/ */
+/* while(j++!=i){ */
+/* SETTCLK; */
+/* _NOP(); */
+/* _NOP(); */
+/* _NOP(); */
+/* CLRTCLK; */
+/* } */
+/* } */
+
+//! Write data to flash memory. Must be preconfigured.
+void jtag430_writeflashword(unsigned int adr, unsigned int data){
+ /*
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x2408);//word write
+ jtag_ir_shift8(IR_ADDR_16BIT);
+ jtag_dr_shift16(adr);
+ jtag_ir_shift8(IR_DATA_TO_ADDR);
+ jtag_dr_shift16(data);
+ SETTCLK;
+
+ //Return to read mode.
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x2409);
+ */
+
+ jtag430_writemem(adr,data);
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x2409);
+
+ //Pulse TCLK
+ jtag430_tclk_flashpulses(35); //35 standard
}
-//! Write data to address.
+//! Configure flash, then write a word.
void jtag430_writeflash(unsigned int adr, unsigned int data){
- //TODO; this is complicated.
+ jtag430_haltcpu();
+
+ //FCTL1=0xA540, enabling flash write
+ jtag430_writemem(0x0128, 0xA540);
+ //FCTL2=0xA540, selecting MCLK as source, DIV=1
+ jtag430_writemem(0x012A, 0xA540);
+ //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
+ jtag430_writemem(0x012C, 0xA500);
+
+ //Write the word itself.
+ jtag430_writeflashword(adr,data);
+
+ //FCTL1=0xA500, disabling flash write
+ jtag430_writemem(0x0128, 0xA500);
+
+ jtag430_releasecpu();
+}
+
+//! Power-On Reset
+void jtag430_por(){
+ unsigned int jtagid;
+
+ // Perform Reset
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x2C01); // apply
+ jtag_dr_shift16(0x2401); // remove
+ CLRTCLK;
+ SETTCLK;
+ CLRTCLK;
+ SETTCLK;
+ CLRTCLK;
+ jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
+ SETTCLK;
+
+ jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
+}
+
+
+
+#define ERASE_GLOB 0xA50E
+#define ERASE_ALLMAIN 0xA50C
+#define ERASE_MASS 0xA506
+#define ERASE_MAIN 0xA504
+#define ERASE_SGMT 0xA502
+
+//! Configure flash, then write a word.
+void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
+ jtag430_haltcpu();
+
+ //FCTL1= erase mode
+ jtag430_writemem(0x0128, mode);
+ //FCTL2=0xA540, selecting MCLK as source, DIV=1
+ jtag430_writemem(0x012A, 0xA540);
+ //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
+ jtag430_writemem(0x012C, 0xA500);
+
+ //Write the erase word.
+ jtag430_writemem(adr, 0x55AA);
+ //Return to read mode.
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x2409);
+
+ //Send the pulses.
+ jtag430_tclk_flashpulses(count);
+
+ //FCTL1=0xA500, disabling flash write
+ jtag430_writemem(0x0128, 0xA500);
+
+ jtag430_releasecpu();
}
SETRST;
P5DIR&=~RST;
delay(0xFFFF);
+
+ //Perform a reset and disable watchdog.
+ jtag430_por();
}
//! Set CPU to Instruction Fetch
void jtag430handle(unsigned char app,
unsigned char verb,
unsigned char len){
- unsigned char i;
switch(verb){
case START:
//Enter JTAG mode.
case JTAG430_WRITEMEM:
case POKE:
jtag430_writemem(cmddataword[0],cmddataword[1]);
- txdata(app,verb,0);
+ cmddataword[0]=jtag430_readmem(cmddataword[0]);
+ txdata(app,verb,2);
break;
case JTAG430_WRITEFLASH:
jtag430_writeflash(cmddataword[0],cmddataword[1]);
+ cmddataword[0]=jtag430_readmem(cmddataword[0]);
+ txdata(app,verb,2);
+ break;
+ case JTAG430_ERASEFLASH:
+ jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
+ jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
+ jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF);
txdata(app,verb,0);
break;
case JTAG430_SETPC:
default:
jtaghandle(app,verb,len);
}
+ jtag430_resettap();
}