+//! Grab the core ID.
+unsigned int jtag430_coreid(){
+ jtag_ir_shift8(IR_COREIP_ID);
+ return jtag_dr_shift16(0);
+}
+
+//! Grab the device ID.
+unsigned long jtag430_deviceid(){
+ jtag_ir_shift8(IR_DEVICE_ID);
+ return jtag_dr_shift20(0);
+}
+
+
+//! Write data to address
+void jtag430x2_writemem(unsigned long adr,
+ unsigned int data){
+ jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
+ if(jtag_dr_shift16(0) & 0x0301){
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ if(adr>=0x100)
+ jtag_dr_shift16(0x0500);//word mode
+ else
+ jtag_dr_shift16(0x0510);//byte mode
+ jtag_ir_shift8(IR_ADDR_16BIT);
+ jtag_dr_shift20(adr);
+
+ SETTCLK;
+
+ jtag_ir_shift8(IR_DATA_TO_ADDR);
+ jtag_dr_shift16(data);//16 word
+
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x0501);
+ SETTCLK;
+
+ CLRTCLK;
+ SETTCLK;
+ //init state
+ }else{
+ while(1) P1OUT^=1; //loop if locked up
+ }
+}
+
+//! Read data from address
+unsigned int jtag430x2_readmem(unsigned long adr){
+ unsigned int toret=0;
+ //unsigned int tries=5;
+
+ while(1){
+ do{
+ jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
+ }while(!(jtag_dr_shift16(0) & 0x0301));
+
+ if(jtag_dr_shift16(0) & 0x0301){
+ // Read Memory
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ if(adr>=0x100){
+ jtag_dr_shift16(0x0501);//word read
+ }else{
+ jtag_dr_shift16(0x0511);//byte read
+ }
+
+ jtag_ir_shift8(IR_ADDR_16BIT);
+ jtag_dr_shift20(adr); //20
+
+ jtag_ir_shift8(IR_DATA_TO_ADDR);
+ SETTCLK;
+ CLRTCLK;
+ toret = jtag_dr_shift16(0x0000);
+
+ SETTCLK;
+
+ //Cycle a bit.
+ CLRTCLK;
+ SETTCLK;
+ return toret;
+ }
+ }
+ //return toret;
+}
+
+//! Syncs a POR.
+unsigned int jtag430x2_syncpor(){
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x1501); //JTAG mode
+ while(!(jtag_dr_shift16(0) & 0x200));
+ return jtag430x2_por();
+}
+
+//! Executes an MSP430X2 POR
+unsigned int jtag430x2_por(){
+ unsigned int i = 0;
+
+ // tick
+ CLRTCLK;
+ SETTCLK;