unsigned long jtag430_deviceid(){
jtag_ir_shift8(IR_DEVICE_ID);
- return jtag_dr_shift(0);
+ return jtag_dr_shift20(0);
}
-//! Set the program counter.
-void jtag430x2_setpc(unsigned long pc){
- unsigned short Mova;
- unsigned short Pc_l;
- Mova = 0x0080;
- Mova += (unsigned short)((pc>>8) & 0x00000F00);
- Pc_l = (unsigned short)((pc & 0xFFFF));
-
- // Check Full-Emulation-State at the beginning
+//! Write data to address
+unsigned int jtag430x2_writemem(unsigned long adr,
+ unsigned long data){
jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
- if(jtag_dr_shift16(0) & 0x0301){
- // MOVA #imm20, PC
- CLRTCLK;
- // take over bus control during clock LOW phase
- jtag_ir_shift8(IR_DATA_16BIT);
- SETTCLK;
- jtag_dr_shift16(Mova);
- jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
- jtag_dr_shift16(0x1400);
- jtag_ir_shift8(IR_DATA_16BIT);
- CLRTCLK;
- SETTCLK;
- jtag_dr_shift16(Pc_l);
- CLRTCLK;
- SETTCLK;
- jtag_dr_shift16(0x4303);
- CLRTCLK;
- jtag_ir_shift8(IR_ADDR_CAPTURE);
- jtag_dr_shift(0x00000);
+ if(jtag_ir_shift8(0) & 0x0301){
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ if(adr>=0x100)
+ jtag_ir_shift8(0x0500);//word mode
+ else
+ jtag_ir_shift8(0x0510);//byte mode
+ jtag_ir_shift8(IR_ADDR_16BIT);
+ jtag_dr_shift20(adr);
+
+ SETTCLK;
+
+ jtag_ir_shift8(IR_DATA_TO_ADDR);
+ jtag_ir_shift8(data);//16 word
+
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_ir_shift8(0x0501);
+ SETTCLK;
+
+ CLRTCLK;
+ SETTCLK;
+ //init state
+ }else{
+ while(1) P1OUT^=1; //loop if locked up
}
}
//! Read data from address
-unsigned int jtag430x2_readmem(unsigned int adr){
- unsigned int toret;
-
- //SETPC_430Xv2(StartAddr);
- SETTCLK;
- jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
- jtag_dr_shift16(0x0501);
- jtag_ir_shift8(IR_ADDR_CAPTURE);
+unsigned int jtag430x2_readmem(unsigned long adr){
+ unsigned int toret=0;
- jtag_ir_shift8(IR_DATA_QUICK);
+ jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
+ if(jtag_dr_shift16(0) & 0x0301){
+ // Read Memory
+ CLRTCLK;
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ if(adr>=0x100){
+ jtag_dr_shift16(0x0501);//word read
+ }else{
+ jtag_dr_shift16(0x0511);//byte read
+ }
+ jtag_ir_shift8(IR_ADDR_16BIT);
+ jtag_dr_shift20(adr); //20
- SETTCLK;
- CLRTCLK;
- toret = jtag_dr_shift16(0);//read
+ jtag_ir_shift8(IR_DATA_TO_ADDR);
+ SETTCLK;
+ CLRTCLK;
+ toret = jtag_dr_shift16(0x0000);
+
+ SETTCLK;
+ // one or more cycle, so CPU is driving correct MAB
- jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
+ CLRTCLK;
+ SETTCLK;
+ // Processor is now again in Init State
+ }else{
+ return 0xDEAD;
+ }
return toret;
}
void jtag430x2handle(unsigned char app,
unsigned char verb,
unsigned char len){
-
+ jtag430_resettap();
switch(verb){
case START:
//Enter JTAG mode.
drwidth=16;
}else if(jtagid==MSP430X2JTAGID){
jtag430mode=MSP430X2MODE;
+ drwidth=20;
}else{
txdata(app,NOK,1);
return;
case JTAG430_READMEM:
case PEEK:
cmddataword[0]=jtag430x2_readmem(cmddataword[0]);
+ //cmddataword[0]=jtag430_readmem(cmddataword[0]);
txdata(app,verb,2);
break;
case JTAG430_COREIP_ID:
case JTAG430_SETINSTRFETCH:
case JTAG430_WRITEMEM:
case POKE:
+ jtag430x2_writemem(cmddataword[0],
+ cmddataword[1]);
+ cmddataword[0]=jtag430x2_readmem(cmddataword[0]);
+ txdata(app,verb,2);
+ break;
case JTAG430_WRITEFLASH:
case JTAG430_ERASEFLASH:
case JTAG430_SETPC: