MSP430X2 support is sufficient to read memory!

[goodfet] / firmware / apps / jtag / jtag430x2.c

diff --git a/firmware/apps/jtag/jtag430x2.c b/firmware/apps/jtag/jtag430x2.c
index e25a905..e496346 100644 (file)
--- a/firmware/apps/jtag/jtag430x2.c
+++ b/firmware/apps/jtag/jtag430x2.c
@@ -53,59 +53,41 @@ unsigned int jtag430_coreid(){
 
 unsigned long jtag430_deviceid(){
   jtag_ir_shift8(IR_DEVICE_ID);
 
 unsigned long jtag430_deviceid(){
   jtag_ir_shift8(IR_DEVICE_ID);

-  return jtag_dr_shift(0);
+  return jtag_dr_shift20(0);

 }
 
 }
 

-//! Set the program counter.
-void jtag430x2_setpc(unsigned long pc){
-  unsigned short Mova;
-  unsigned short Pc_l;

 
 

-  Mova  = 0x0080;
-  Mova += (unsigned short)((pc>>8) & 0x00000F00);
-  Pc_l  = (unsigned short)((pc & 0xFFFF));
+//! Read data from address
+unsigned int jtag430x2_readmem(unsigned long adr){
+  unsigned int toret=0;

 
 

-  // Check Full-Emulation-State at the beginning                                                                                                                                   

   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
   if(jtag_dr_shift16(0) & 0x0301){
   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
   if(jtag_dr_shift16(0) & 0x0301){

-      // MOVA #imm20, PC                                                                                                                                                             
-      CLRTCLK;
-      // take over bus control during clock LOW phase                                                                                                                                
-      jtag_ir_shift8(IR_DATA_16BIT);
-      SETTCLK;
-      jtag_dr_shift16(Mova);
-      jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
-      jtag_dr_shift16(0x1400);
-      jtag_ir_shift8(IR_DATA_16BIT);
-      CLRTCLK;
-      SETTCLK;
-      jtag_dr_shift16(Pc_l);
-      CLRTCLK;
-      SETTCLK;
-      jtag_dr_shift16(0x4303);
-      CLRTCLK;
-      jtag_ir_shift8(IR_ADDR_CAPTURE);
-      jtag_dr_shift(0x00000);
-  }
-}
+    // Read Memory                                                                                                                                                                 
+    CLRTCLK;
+    jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+    if(adr>=0x100){
+      jtag_dr_shift16(0x0501);//word read
+    }else{
+      jtag_dr_shift16(0x0511);//byte read
+    }
+    jtag_ir_shift8(IR_ADDR_16BIT);
+    jtag_dr_shift20(adr);

 
 

-//! Read data from address
-unsigned int jtag430x2_readmem(unsigned int adr){
-  unsigned int toret;
-  
-  //SETPC_430Xv2(StartAddr);
-  SETTCLK;
-  jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
-  jtag_dr_shift16(0x0501);
-  jtag_ir_shift8(IR_ADDR_CAPTURE);
+    jtag_ir_shift8(IR_DATA_TO_ADDR);
+    SETTCLK;
+    CLRTCLK;
+    toret = jtag_dr_shift16(0x0000);
+    
+    SETTCLK;
+    // one or more cycle, so CPU is driving correct MAB

 
 

-  jtag_ir_shift8(IR_DATA_QUICK);
+    CLRTCLK;
+    SETTCLK;
+    // Processor is now again in Init State
+  }

 
 

-  SETTCLK;
-  CLRTCLK;
-  toret = jtag_dr_shift16(0);//read

 
 

-  jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);

   
   return toret;
 }
   
   return toret;
 }


@@ -128,6 +110,7 @@ void jtag430x2handle(unsigned char app,
       drwidth=16;
     }else if(jtagid==MSP430X2JTAGID){
       jtag430mode=MSP430X2MODE;
       drwidth=16;
     }else if(jtagid==MSP430X2JTAGID){
       jtag430mode=MSP430X2MODE;

+      drwidth=20;

     }else{
       txdata(app,NOK,1);
       return;
     }else{
       txdata(app,NOK,1);
       return;


@@ -140,6 +123,7 @@ void jtag430x2handle(unsigned char app,
   case JTAG430_READMEM:
   case PEEK:
     cmddataword[0]=jtag430x2_readmem(cmddataword[0]);
   case JTAG430_READMEM:
   case PEEK:
     cmddataword[0]=jtag430x2_readmem(cmddataword[0]);

+    //cmddataword[0]=jtag430_readmem(cmddataword[0]);

     txdata(app,verb,2);
     break;
   case JTAG430_COREIP_ID:
     txdata(app,verb,2);
     break;
   case JTAG430_COREIP_ID: