Improving CC2420 packet reception.

[goodfet] / firmware / apps / jtag / jtagarm7.c

diff --git a/firmware/apps/jtag/jtagarm7.c b/firmware/apps/jtag/jtagarm7.c
index 8cd4c26..6587de1 100644 (file)
--- a/firmware/apps/jtag/jtagarm7.c
+++ b/firmware/apps/jtag/jtagarm7.c
@@ -80,17 +80,18 @@ http://hri.sourceforge.net/tools/jtag_faq_org.html
 
 // ! Start JTAG, setup pins, reset TAP and return IDCODE
 void jtagarm7tdmi_start() {
-  jtagsetup();
+  jtag_setup();
   SETTST;
-  jtag_resettap();
+  jtag_reset_tap();
 }
 
 
 u8 jtagarm_shift_ir(u8 ir, u8 flags){
   u8 retval = 0;
   if (last_ir != ir){
-    jtag_goto_shift_ir();
-    retval = jtagtransn(ir, 4, LSB|flags); 
+       jtag_capture_ir();
+       jtag_shift_register();
+    retval = jtag_trans_n(ir, 4, LSB|flags); 
     tapstate = RunTest_Idle;
     last_ir = ir;
   }
@@ -109,8 +110,9 @@ state” to the “Select DR” state each time the “Update” state is reache
   if (last_scanchain != chain){
     jtagarm_shift_ir(ARM7TDMI_IR_SCAN_N, NORETIDLE);
     last_scanchain = chain;
-    jtag_goto_shift_dr();
-    retval = jtagtransn(chain, 4, LSB | NORETIDLE);
+       jtag_capture_dr();
+       jtag_shift_register();
+    retval = jtag_trans_n(chain, 4, LSB | NORETIDLE);
     tapstate = Update_DR;
   }
   jtagarm_shift_ir(testmode, NORETIDLE); 
@@ -123,10 +125,11 @@ state” to the “Select DR” state each time the “Update” state is reache
 unsigned long eice_write(unsigned char reg, unsigned long data){
   unsigned long retval, temp;
   jtagarm7tdmi_scan(2, ARM7TDMI_IR_INTEST);
-  jtag_goto_shift_dr();
-  retval = jtagtransn(data, 32, LSB| NOEND| NORETIDLE);         // send in the data - 32-bits lsb
-  temp = jtagtransn(reg, 5, LSB| NOEND| NORETIDLE);             // send in the register address - 5 bits lsb
-  jtagtransn(1, 1, LSB);                                        // send in the WRITE bit
+  jtag_capture_dr();
+  jtag_shift_register();
+  retval = jtag_trans_n(data, 32, LSB| NOEND| NORETIDLE);         // send in the data - 32-bits lsb
+  temp = jtag_trans_n(reg, 5, LSB| NOEND| NORETIDLE);             // send in the register address - 5 bits lsb
+  jtag_trans_n(1, 1, LSB);                                        // send in the WRITE bit
   tapstate = RunTest_Idle;
   return(retval); 
 }
@@ -135,11 +138,13 @@ unsigned long eice_write(unsigned char reg, unsigned long data){
 unsigned long eice_read(unsigned char reg){               // PROVEN
   unsigned long temp, retval;
   jtagarm7tdmi_scan(2, ARM7TDMI_IR_INTEST);
-  jtag_goto_shift_dr();                                         // send in the register address - 5 bits LSB
-  temp = jtagtransn(reg, 5, LSB| NOEND| NORETIDLE);
-  jtagtransn(0L, 1, LSB);                                       // clear TDI to select "read only"
-  jtag_goto_shift_dr();                                         // Now shift out the 32 bits
-  retval = jtagtransn(0L, 32, LSB);                             // atmel arm jtag docs pp.10-11: LSB first
+  jtag_capture_dr();
+  jtag_shift_register(); // send in the register address - 5 bits LSB
+  temp = jtag_trans_n(reg, 5, LSB| NOEND| NORETIDLE);
+  jtag_trans_n(0L, 1, LSB);                                       // clear TDI to select "read only"
+  jtag_capture_dr();
+  jtag_shift_register(); // Now shift out the 32 bits
+  retval = jtag_trans_n(0L, 32, LSB);                             // atmel arm jtag docs pp.10-11: LSB first
   tapstate = RunTest_Idle;
   return(retval);
   
@@ -152,7 +157,8 @@ unsigned long jtagarm7tdmi_instr_primitive(unsigned long instr, char breakpt){
 
   //debughex32(instr);
   if (last_instr != instr && last_sysstate != breakpt){
-    jtag_goto_shift_dr();
+         jtag_capture_dr();
+         jtag_shift_register();
     // if the next instruction is to run using MCLK (master clock), set TDI
     if (breakpt)
       {
@@ -165,7 +171,7 @@ unsigned long jtagarm7tdmi_instr_primitive(unsigned long instr, char breakpt){
     jtag_tcktock();
     
     // Now shift in the 32 bits
-    retval = jtagtransn(instr, 32, 0);    // Must return to RUN-TEST/IDLE state for instruction to enter pipeline, and causes debug clock.
+    retval = jtag_trans_n(instr, 32, 0);    // Must return to RUN-TEST/IDLE state for instruction to enter pipeline, and causes debug clock.
     tapstate = RunTest_Idle;
     last_instr = instr;
     last_sysstate = breakpt;
@@ -294,22 +300,24 @@ void jtagarm7_handle_fn( uint8_t const app,
     txdata(app,verb,1);
     break;
   case JTAG_DR_SHIFT:
-    jtag_goto_shift_dr();
-    cmddatalong[0] = jtagtransn(cmddatalong[1],cmddata[0],cmddata[1]);
+       jtag_capture_dr();
+       jtag_shift_register();
+    cmddatalong[0] = jtag_trans_n(cmddatalong[1],cmddata[0],cmddata[1]);
     tapstate = (cmddata[1]&NORETIDLE)>0?Update_DR:RunTest_Idle;
     txdata(app,verb,4);
     break;
   case JTAGARM7_CHAIN0:
     jtagarm7tdmi_scan(0, ARM7TDMI_IR_INTEST);
-    jtag_goto_shift_dr();
+       jtag_capture_dr();
+       jtag_shift_register();
     //debughex32(cmddatalong[0]);
     //debughex(cmddataword[4]);
     //debughex32(cmddatalong[1]);
     //debughex32(cmddatalong[3]);
-    cmddatalong[0] = jtagtransn(cmddatalong[0], 32, LSB| NOEND| NORETIDLE);
-    cmddatalong[2] = jtagtransn(cmddataword[4], 9, MSB| NOEND| NORETIDLE);
-    cmddatalong[1] = jtagtransn(cmddatalong[1], 32, MSB| NOEND| NORETIDLE);
-    cmddatalong[3] = jtagtransn(cmddatalong[3], 32, MSB);
+    cmddatalong[0] = jtag_trans_n(cmddatalong[0], 32, LSB| NOEND| NORETIDLE);
+    cmddatalong[2] = jtag_trans_n(cmddataword[4], 9, MSB| NOEND| NORETIDLE);
+    cmddatalong[1] = jtag_trans_n(cmddatalong[1], 32, MSB| NOEND| NORETIDLE);
+    cmddatalong[3] = jtag_trans_n(cmddatalong[3], 32, MSB);
     tapstate = RunTest_Idle;
     txdata(app,verb,16);
     break;
@@ -335,7 +343,7 @@ void jtagarm7_handle_fn( uint8_t const app,
     jtagarm7tdmi_set_register(cmddatalong[1], cmddatalong[0]);
     txdata(app,verb,4);
     break;
-  case JTAG_RESETTARGET:
+  case JTAG_RESET_TARGET:
     //FIXME: BORKEN
     debugstr("RESET TARGET");
     CLRTST;