/*! \file jtagarm7tdmi.c
- \brief ARM7TDMI JTAG (AT91R40008)
+ \brief ARM7TDMI JTAG (AT91R40008, AT91SAM7xxx)
*/
#include "platform.h"
}
void jtag_arm_tcktock() {
+ delay(100); // FIXME: Should never wait this long...
CLRTCK;
PLEDOUT^=PLEDPIN;
+ delay(100); // FIXME: Should never wait this long...
SETTCK;
PLEDOUT^=PLEDPIN;
}
// ! Start JTAG, setup pins, reset TAP and return IDCODE
unsigned long jtagarm7tdmi_start() {
jtagsetup();
- //Known-good starting position.
- //Might be unnecessary.
- //SETTST;
- //SETRST;
-
- //delay(0x2);
-
- //CLRRST;
- //delay(2);
- //CLRTST;
-
- //msdelay(10);
- //SETRST;
- /*
- P5DIR &=~RST;
- */
- //delay(0x2);
jtagarm7tdmi_resettap();
return jtagarm7tdmi_idcode();
}
unsigned long high = 1;
unsigned long mask;
- for (bit=(bitcount-1)/8; bit>0; bit--)
- high <<= 8;
- high <<= ((bitcount-1)%8);
+ //for (bit=(bitcount-1)/8; bit>0; bit--)
+ // high <<= 8;
+ //high <<= ((bitcount-1)%8);
+ high <<= (bitcount-1);
mask = high-1;
//! Connect Bypass Register to TDO/TDI
unsigned char jtagarm7tdmi_bypass(){ // PROVEN
- //jtagarm7tdmi_resettap();
+ jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_BYPASS, 4, LSB, END, NORETIDLE);
}
//! INTEST verb - do internal test
unsigned char jtagarm7tdmi_intest() {
- //jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_INTEST, 4, LSB, END, NORETIDLE);
}
//! EXTEST verb
unsigned char jtagarm7tdmi_extest() {
- //jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_EXTEST, 4, LSB, END, NORETIDLE);
}
//! RESTART verb
unsigned char jtagarm7tdmi_restart() {
- //jtagarm7tdmi_resettap();
+ jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_RESTART, 4, LSB, END, RETIDLE);
}
state” to the “Select DR” state each time the “Update” state is reached.
*/
unsigned long retval;
- if (current_chain != chain) { // breaks shit when going from idcode back to scan chain
+ if (current_chain != chain) {
+ //debugstr("===change chains===");
SHIFT_IR;
jtagarmtransn(ARM7TDMI_IR_SCAN_N, 4, LSB, END, NORETIDLE);
SHIFT_DR;
retval = jtagarmtransn(chain, 4, LSB, END, NORETIDLE);
current_chain = chain;
} else
+ //debugstr("===NOT change chains===");
retval = current_chain;
// put in test mode...
SHIFT_IR;
//! push an instruction into the pipeline
-unsigned long jtagarm7tdmi_instr_primitive(unsigned long instr, char breakpt){
+unsigned long jtagarm7tdmi_instr_primitive(unsigned long instr, char breakpt){ // PROVEN
unsigned long retval;
- //jtagarm7tdmi_resettap(); // FIXME: DEBUG: seems necessary for some reason. ugh.
jtagarm7tdmi_scan_intest(1);
SHIFT_DR;
// Now shift in the 32 bits
retval = jtagarmtransn(instr, 32, MSB, END, RETIDLE); // Must return to RUN-TEST/IDLE state for instruction to enter pipeline, and causes debug clock.
- //jtag_arm_tcktock();
return(retval);
}
-
-unsigned long jtagarm7tdmi_nop(char breakpt){
+//! push NOP into the instruction pipeline
+unsigned long jtagarm7tdmi_nop(char breakpt){ // PROVEN
return jtagarm7tdmi_instr_primitive(ARM_INSTR_NOP, breakpt);
}
NOP
*/
+
//! set the current mode to ARM, returns PC (FIXME). Should be used by haltcpu(), which should also store PC and the THUMB state, for use by releasecpu();
unsigned long jtagarm7tdmi_setMode_ARM(){ // PROVEN
+ debugstr("=== Thumb Mode... Switching to ARM mode ===");
unsigned long retval = 0xff;
while ((jtagarm7tdmi_get_dbgstate() & JTAG_ARM7TDMI_DBG_TBIT)&& retval-- > 0){
cmddataword[6] = jtagarm7tdmi_instr_primitive(THUMB_INSTR_NOP,0);
//! shifter for writing to chain2 (EmbeddedICE).
unsigned long eice_write(unsigned char reg, unsigned long data){
unsigned long retval, temp;
+ debugstr("eice_write");
+ debughex(reg);
+ debughex32(data);
jtagarm7tdmi_scan_intest(2);
// Now shift in the 32 bits
SHIFT_DR;
//! shifter for reading from chain2 (EmbeddedICE).
unsigned long eice_read(unsigned char reg){ // PROVEN
- unsigned long temp;
+ unsigned long temp, retval;
+ debugstr("eice_read");
+ debughex(reg);
jtagarm7tdmi_scan_intest(2);
// send in the register address - 5 bits LSB
SHIFT_DR;
// Now shift out the 32 bits
- return(jtagarmtransn(0, 32, LSB, END, RETIDLE)); // atmel arm jtag docs pp.10-11: LSB first
+ retval = jtagarmtransn(0, 32, LSB, END, RETIDLE); // atmel arm jtag docs pp.10-11: LSB first
+ debughex32(retval);
+ return(retval); // atmel arm jtag docs pp.10-11: LSB first
}
//! Retrieve a 32-bit Register value
unsigned long jtagarm7tdmi_get_register(unsigned long reg) {
- unsigned long retval = 0, instr;
+ unsigned long retval = 0, instr, reg2;
+ reg2 = (reg&0xf);
// push nop into pipeline - clean out the pipeline...
instr = (unsigned long)(reg<<12) | (unsigned long)ARM_READ_REG; // STR Rx, [R14]
+ instr |= (unsigned long)((unsigned long)reg2<<8)<<8;
//instr = (unsigned long)(((unsigned long)reg<<12) | ARM_READ_REG);
+ //debugstr("Reading:");
debughex32(instr);
+ jtagarm7tdmi_nop( 0);
+ jtagarm7tdmi_nop( 0);
jtagarm7tdmi_nop( 0);
jtagarm7tdmi_instr_primitive(instr, 0);
jtagarm7tdmi_nop( 0); // push nop into pipeline - fetched
//! Set a 32-bit Register value
void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val) {
- unsigned long instr;
+ unsigned long instr, reg2;
+ reg2 = (reg&0xf);
instr = (unsigned long)(((unsigned long)reg<<12) | ARM_WRITE_REG); // LDR Rx, [R14]
- debugstr("Writing:");
+ instr |= (unsigned long)((unsigned long)reg2<<8)<<8;
+ //instr |= (unsigned long)((((unsigned long)reg)&0x7)<<8)<<8;
+ //debugstr("Writing:");
debughex32(instr);
- debughex32(val);
+ //debughex32(val);
+ jtagarm7tdmi_nop( 0); // push nop into pipeline - clean out the pipeline...
jtagarm7tdmi_nop( 0); // push nop into pipeline - clean out the pipeline...
jtagarm7tdmi_instr_primitive(instr, 0); // push instr into pipeline - fetch
jtagarm7tdmi_nop( 0); // push nop into pipeline - decode
- jtagarm7tdmi_nop( 0); // push nop into pipeline - execute
+ //jtagarm7tdmi_nop( 0); // push nop into pipeline - execute
- //debughex32(jtagarm7tdmi_instr_primitive(val, 0)); // push 32-bit word on data bus
+ jtagarm7tdmi_instr_primitive(val, 0); // push 32-bit word on data bus
+ jtagarm7tdmi_instr_primitive(val, 0); // push 32-bit word on data bus
jtagarm7tdmi_instr_primitive(val, 0); // push 32-bit word on data bus
jtagarm7tdmi_nop( 0); // push nop into pipeline - executed
+ jtagarm7tdmi_nop( 0); // push nop into pipeline - executed
- //if (reg == ARM_REG_PC){
+ if (reg == ARM_REG_PC){
jtagarm7tdmi_nop( 0);
jtagarm7tdmi_nop( 0);
- //}
+ }
jtagarm7tdmi_nop( 0);
}
//! Get all registers, placing them into cmddatalong[0-15]
void jtagarm7tdmi_get_registers() {
+ debugstr("First 8 registers:");
+ debugstr(" Instr and the first few pops from the instruction chain:");
debughex32(ARM_INSTR_SKANKREGS1);
debughex32(jtagarm7tdmi_nop( 0));
debughex32(jtagarm7tdmi_instr_primitive(ARM_INSTR_SKANKREGS1,0));
cmddatalong[ 5] = jtagarm7tdmi_nop( 0);
cmddatalong[ 6] = jtagarm7tdmi_nop( 0);
cmddatalong[ 7] = jtagarm7tdmi_nop( 0);
+
+ debugstr("Last 8 registers:");
+ debugstr(" Instr and the first few pops from the instruction chain:");
debughex32(ARM_INSTR_SKANKREGS2);
debughex32(jtagarm7tdmi_nop( 0));
//jtagarm7tdmi_nop( 0);
unsigned long jtagarm7tdmi_haltcpu(){ // PROVEN
int waitcount = 0xfff;
+/******** OLD WAY ********/
// store watchpoint info? - not right now
eice_write(EICE_WP1ADDR, 0); // write 0 in watchpoint 1 address
eice_write(EICE_WP1ADDRMASK, 0xffffffff); // write 0xffffffff in watchpoint 1 address mask
eice_write(EICE_WP1DATA, 0); // write 0 in watchpoint 1 data
eice_write(EICE_WP1DATAMASK, 0xffffffff); // write 0xffffffff in watchpoint 1 data mask
- eice_write(EICE_WP1CTRL, 0x100); //!!!!! WTF! THIS IS SUPPOSED TO BE 9 bits wide?!? // write 0x00000100 in watchpoint 1 control value register (enables watchpoint)
- eice_write(EICE_WP1CTRLMASK, 0xfffffff7); //!!!!! WTF! THIS IS SUPPOSED TO BE 8 bits wide?!? // write 0xfffffff7 in watchpoint 1 control mask - only detect the fetch instruction
+ eice_write(EICE_WP1CTRL, 0x100); // write 0x00000100 in watchpoint 1 control value register (enables watchpoint)
+ eice_write(EICE_WP1CTRLMASK, 0xfffffff7); // write 0xfffffff7 in watchpoint 1 control mask - only detect the fetch instruction
+/***************************/
+
+/******** NEW WAY *********/
+// eice_write(EICE_DBGCTRL, JTAG_ARM7TDMI_DBG_DBGRQ); // r/o register?
+/****************************/
// poll until debug status says the cpu is in debug mode
while (!(jtagarm7tdmi_get_dbgstate() & 0x1) && waitcount-- > 0){
delay(1);
}
+
+/******** OLD WAY ********/
eice_write(EICE_WP1CTRL, 0x0); // write 0 in watchpoint 0 control value - disables watchpoint 0
+/***************************/
+
+/******** NEW WAY ********/
+// eice_write(EICE_DBGCTRL, 0); // r/o register?
+/***************************/
// store the debug state
last_halt_debug_state = jtagarm7tdmi_get_dbgstate();
jtagarm7tdmi_resettap();
val = cmddata[0];
cmddatalong[0] = jtagarm7tdmi_get_register(val);
+ //debughex32(cmddatalong[0]);
txdata(app,verb,4);
break;
case JTAGARM7TDMI_SET_REGISTER: // FIXME: NOT AT ALL CORRECT, THIS IS TESTING CODE ONLY
jtagarm7tdmi_resettap();
+ debughex32(cmddatalong[1]);
jtagarm7tdmi_set_register(cmddata[0], cmddatalong[1]);
cmddatalong[0] = cmddatalong[1];
txdata(app,verb,4);
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